SimpleCPU compiles with merge.

arch/alpha/isa_traits.hh:
arch/alpha/linux/process.cc:
arch/alpha/process.cc:
arch/alpha/process.hh:
arch/alpha/tru64/process.cc:
base/chunk_generator.hh:
base/loader/elf_object.cc:
cpu/cpu_exec_context.cc:
cpu/cpu_exec_context.hh:
cpu/exec_context.hh:
cpu/simple/cpu.cc:
kern/linux/linux.hh:
kern/tru64/tru64.hh:
mem/packet.hh:
mem/page_table.cc:
mem/page_table.hh:
mem/physical.cc:
mem/request.hh:
mem/translating_port.cc:
sim/process.hh:
sim/system.cc:
    Fixing merged changes.

--HG--
extra : convert_revision : 2e94f21009395db654880fcb94ec806b6f5772c3

4 files changed, 19 insertions, 23 deletions

diff --git a/cpu/cpu_exec_context.cc b/cpu/cpu_exec_context.cc
index 6ef42762d..f840c38dc 100644
--- a/cpu/cpu_exec_context.cc
+++ b/cpu/cpu_exec_context.cc
@@ -92,7 +92,7 @@ CPUExecContext::CPUExecContext(BaseCPU *_cpu, int _thread_num,
 }
 
 CPUExecContext::CPUExecContext(RegFile *regFile)
-    : cpu(NULL), thread_num(-1), process(NULL), mem(NULL), asid(-1),
+    : cpu(NULL), thread_num(-1), process(NULL), asid(-1),
       func_exe_inst(0), storeCondFailures(0)
 {
     regs = *regFile;
diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh
index e17cfbb94..6f725d1e4 100644
--- a/cpu/cpu_exec_context.hh
+++ b/cpu/cpu_exec_context.hh
@@ -363,15 +363,13 @@ class CPUExecContext
     {
         panic("instRead not implemented");
         // return funcPhysMem->read(req, inst);
-        return No_Fault;
+        return NoFault;
     }
 
     void setCpuId(int id) { cpu_id = id; }
 
     int readCpuId() { return cpu_id; }
 
-    FunctionalMemory *getMemPtr() { return mem; }
-
     void copyArchRegs(ExecContext *xc);
 
     //
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 2b6c41bd7..c917b46e9 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -30,7 +30,7 @@
 #define __CPU_EXEC_CONTEXT_HH__
 
 #include "config/full_system.hh"
-#include "mem/mem_req.hh"
+#include "mem/request.hh"
 #include "sim/faults.hh"
 #include "sim/host.hh"
 #include "sim/serialize.hh"
@@ -43,8 +43,8 @@ class AlphaDTB;
 class AlphaITB;
 class BaseCPU;
 class Event;
-class FunctionalMemory;
 class PhysicalMemory;
+class TranslatingPort;
 class Process;
 class System;
 
@@ -79,6 +79,8 @@ class ExecContext
         Halted
     };
 
+    TranslatingPort * port;
+
     virtual ~ExecContext() { };
 
     virtual BaseCPU *getCpuPtr() = 0;
@@ -87,8 +89,6 @@ class ExecContext
 
     virtual int readCpuId() = 0;
 
-    virtual FunctionalMemory *getMemPtr() = 0;
-
 #if FULL_SYSTEM
     virtual System *getSystemPtr() = 0;
 
@@ -148,11 +148,11 @@ class ExecContext
     virtual int getInstAsid() = 0;
     virtual int getDataAsid() = 0;
 
-    virtual Fault translateInstReq(MemReqPtr &req) = 0;
+    virtual Fault translateInstReq(CpuRequestPtr &req) = 0;
 
-    virtual Fault translateDataReadReq(MemReqPtr &req) = 0;
+    virtual Fault translateDataReadReq(CpuRequestPtr &req) = 0;
 
-    virtual Fault translateDataWriteReq(MemReqPtr &req) = 0;
+    virtual Fault translateDataWriteReq(CpuRequestPtr &req) = 0;
 
     // Also somewhat obnoxious.  Really only used for the TLB fault.
     // However, may be quite useful in SPARC.
@@ -249,8 +249,6 @@ class ProxyExecContext : public ExecContext
 
     int readCpuId() { return actualXC->readCpuId(); }
 
-    FunctionalMemory *getMemPtr() { return actualXC->getMemPtr(); }
-
 #if FULL_SYSTEM
     System *getSystemPtr() { return actualXC->getSystemPtr(); }
 
@@ -310,13 +308,13 @@ class ProxyExecContext : public ExecContext
     int getInstAsid() { return actualXC->getInstAsid(); }
     int getDataAsid() { return actualXC->getDataAsid(); }
 
-    Fault translateInstReq(MemReqPtr &req)
+    Fault translateInstReq(CpuRequestPtr &req)
     { return actualXC->translateInstReq(req); }
 
-    Fault translateDataReadReq(MemReqPtr &req)
+    Fault translateDataReadReq(CpuRequestPtr &req)
     { return actualXC->translateDataReadReq(req); }
 
-    Fault translateDataWriteReq(MemReqPtr &req)
+    Fault translateDataWriteReq(CpuRequestPtr &req)
     { return actualXC->translateDataWriteReq(req); }
 
     // @todo: Do I need this?
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index fc70df662..4ac8c845c 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -410,7 +410,7 @@ SimpleCPU::copySrcTranslate(Addr src)
     }
     return fault;
 #else
-    return No_Fault;
+    return NoFault;
 #endif
 }
 
@@ -462,7 +462,7 @@ SimpleCPU::copy(Addr dest)
     return fault;
 #else
     panic("copy not implemented");
-    return No_Fault;
+    return NoFault;
 #endif
 }
 
@@ -483,7 +483,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
         }
 
         // @todo: Figure out a way to create a Fault from the packet result.
-        return No_Fault;
+        return NoFault;
     }
 
 //    memReq->reset(addr, sizeof(T), flags);
@@ -501,7 +501,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
     Fault fault = cpuXC->translateDataReadReq(data_read_req);
 
     // Now do the access.
-    if (fault == No_Fault) {
+    if (fault == NoFault) {
 #if SIMPLE_CPU_MEM_TIMING
         data_read_pkt = new Packet;
         data_read_pkt->cmd = Read;
@@ -525,7 +525,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
         }
 
         // @todo: Figure out a way to create a Fault from the packet result.
-        return No_Fault;
+        return NoFault;
 #endif
     }
 /*
@@ -616,7 +616,7 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
     // translate to physical address
     Fault fault = cpuXC->translateDataWriteReq(data_write_req);
     // Now do the access.
-    if (fault == No_Fault) {
+    if (fault == NoFault) {
 #if SIMPLE_CPU_MEM_TIMING
         data_write_pkt = new Packet;
         data_write_pkt->cmd = Write;
@@ -974,7 +974,7 @@ SimpleCPU::tick()
                      IFETCH_FLAGS(xc->regs.pc));
 */
 
-        fault = xc->translateInstReq(ifetch_req);
+        fault = cpuXC->translateInstReq(ifetch_req);
 
         if (fault == NoFault) {
 #if SIMPLE_CPU_MEM_TIMING