diff options
| author | Kevin Lim <ktlim@umich.edu> | 2006-04-24 16:59:50 -0400 |
|---|---|---|
| committer | Kevin Lim <ktlim@umich.edu> | 2006-04-24 16:59:50 -0400 |
| commit | b14bf0321947419603610f07ed4f14b51a2192a3 (patch) | |
| tree | 45fa28b476126fba7788ba01a4ce04057447f1a5 /cpu | |
| parent | b363a3703da7f9773f4afe2469c0206e14de1813 (diff) | |
| download | gem5-b14bf0321947419603610f07ed4f14b51a2192a3.tar.xz | |
Fixes for ll/sc for the O3 model.
cpu/o3/alpha_cpu.hh:
Store conditionals should not write their data to memory if they failed.
cpu/o3/lsq_unit.hh:
Setup request parameters when they're needed.
--HG--
extra : convert_revision : d75cd7deda03584b7e25cb567e4d79032cac7118
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/o3/alpha_cpu.hh | 3 | ||||
| -rw-r--r-- | cpu/o3/lsq_unit.hh | 6 |
2 files changed, 5 insertions, 4 deletions
diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh index 68e149e77..dfdf092ed 100644 --- a/cpu/o3/alpha_cpu.hh +++ b/cpu/o3/alpha_cpu.hh @@ -425,9 +425,10 @@ class AlphaFullCPU : public FullO3CPU<Impl> req->result = 2; } else { if (this->lockFlag/* && this->lockAddr == req->paddr*/) { - req->result=1; + req->result = 1; } else { req->result = 0; + return NoFault; } } } diff --git a/cpu/o3/lsq_unit.hh b/cpu/o3/lsq_unit.hh index 73c485ce9..ba8b1d2e2 100644 --- a/cpu/o3/lsq_unit.hh +++ b/cpu/o3/lsq_unit.hh @@ -566,6 +566,9 @@ LSQUnit<Impl>::read(MemReqPtr &req, T &data, int load_idx) DPRINTF(LSQUnit, "Doing functional access for inst PC %#x\n", loadQueue[load_idx]->readPC()); assert(!req->data); + req->cmd = Read; + req->completionEvent = NULL; + req->time = curTick; req->data = new uint8_t[64]; Fault fault = cpu->read(req, data); memcpy(req->data, &data, sizeof(T)); @@ -587,9 +590,6 @@ LSQUnit<Impl>::read(MemReqPtr &req, T &data, int load_idx) } DPRINTF(LSQUnit, "Doing timing access for inst PC %#x\n", loadQueue[load_idx]->readPC()); - req->cmd = Read; - req->completionEvent = NULL; - req->time = curTick; assert(!req->completionEvent); req->completionEvent = |