Make the notion of a global event tick independent of the actual

CPU cycle ticks.  This allows the user to have CPUs of different
frequencies, and also allows frequencies and latencies that are
not evenly divisible by the CPU frequency.  For now, the CPU
frequency is still set to the global frequency, but soon, we'll
hopefully make the global frequency fixed at something like 1THz
and set all other frequencies independently.

arch/alpha/ev5.cc:
    The cycles counter is based on the current cpu cycle.
cpu/base_cpu.cc:
    frequency isn't the cpu parameter anymore, cycleTime is.
cpu/base_cpu.hh:
    frequency isn't the cpu parameter anymore, cycleTime is.
    create several public functions for getting the cpu frequency
    and the numbers of ticks for a given number of cycles, etc.
cpu/memtest/memtest.cc:
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
cpu/trace/trace_cpu.cc:
    Now that ticks aren't cpu cycles, fixup code to advance
    by the proper number of ticks.
cpu/memtest/memtest.hh:
cpu/trace/trace_cpu.hh:
    Provide a function to get the number of ticks for a given
    number of cycles.
dev/alpha_console.cc:
    Update for changes in the way that frequencies and latencies are
    accessed.  Move some stuff to init()
dev/alpha_console.hh:
    Need a pointer to the system and the cpu to get the frequency
    so we can pass the info to the console code.
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/ethertap.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/ns_gige.hh:
    update for changes in the way bandwidths are passed from
    python to C++ to accomidate the new way that ticks works.
dev/ide_disk.cc:
    update for changes in the way bandwidths are passed from
    python to C++ to accomidate the new way that ticks works.
    Add some extra debugging printfs
dev/platform.cc:
dev/sinic.cc:
dev/sinic.hh:
    outline the constructor and destructor
dev/platform.hh:
    outline the constructor and destructor.
    don't keep track of the interrupt frequency.  Only provide the
    accessor function.
dev/tsunami.cc:
dev/tsunami.hh:
    outline the constructor and destructor
    Don't set the interrupt frequency here.  Get it from the actual device
    that does the interrupting.
dev/tsunami_io.cc:
dev/tsunami_io.hh:
    Make the interrupt interval a configuration parameter.  (And convert
    the interval to the new latency/frequency stuff in the python)
kern/linux/linux_system.cc:
    update for changes in the way bandwidths are passed from
    python to C++ to accomidate the new way that ticks works.
    For now, we must get the boot cpu's frequency as a parameter
    since allowing the system to have a pointer to the boot cpu would
    cause a cycle.
kern/tru64/tru64_system.cc:
    For now, we must get the boot cpu's frequency as a parameter
    since allowing the system to have a pointer to the boot cpu would
    cause a cycle.
python/m5/config.py:
    Fix support for cycle_time relative latencies and frequencies.
    Add support for getting a NetworkBandwidth or a MemoryBandwidth.
python/m5/objects/BaseCPU.mpy:
    All CPUs now have a cycle_time.  The default is the global frequency,
    but it is now possible to set the global frequency to some large value
    (like 1THz) and set each CPU frequency independently.
python/m5/objects/BaseCache.mpy:
python/m5/objects/Ide.mpy:
    Make this a Latency parameter
python/m5/objects/BaseSystem.mpy:
    We need to pass the boot CPU's frequency to the system
python/m5/objects/Ethernet.mpy:
    Update parameter types to use latency and bandwidth types
python/m5/objects/Platform.mpy:
    this frequency isn't needed.  We get it from the clock interrupt.
python/m5/objects/Tsunami.mpy:
    The clock generator should hold the frequency
sim/eventq.hh:
    Need to remove this assertion because the writeback event
    queue is different from the CPU's event queue which can cause
    this assertion to fail.
sim/process.cc:
    Fix comment.
sim/system.hh:
    Struct member to hold the boot CPU's frequency.
sim/universe.cc:
    remove unneeded variable.

--HG--
extra : convert_revision : 51efe4041095234bf458d9b3b0d417f4cae16fdc

8 files changed, 28 insertions, 14 deletions

diff --git a/cpu/base_cpu.cc b/cpu/base_cpu.cc
index 74e57baa6..9d94c575c 100644
--- a/cpu/base_cpu.cc
+++ b/cpu/base_cpu.cc
@@ -51,11 +51,12 @@ int maxThreadsPerCPU = 1;
 
 #ifdef FULL_SYSTEM
 BaseCPU::BaseCPU(Params *p)
-    : SimObject(p->name), frequency(p->freq), checkInterrupts(true),
+    : SimObject(p->name), cycleTime(p->cycleTime), checkInterrupts(true),
       params(p), number_of_threads(p->numberOfThreads), system(p->system)
 #else
 BaseCPU::BaseCPU(Params *p)
-    : SimObject(p->name), params(p), number_of_threads(p->numberOfThreads)
+    : SimObject(p->name), cycleTime(p->cycleTime), params(p),
+      number_of_threads(p->numberOfThreads)
 #endif
 {
     // add self to global list of CPUs
diff --git a/cpu/base_cpu.hh b/cpu/base_cpu.hh
index f346f4ec5..ea12460db 100644
--- a/cpu/base_cpu.hh
+++ b/cpu/base_cpu.hh
@@ -46,9 +46,17 @@ class ExecContext;
 
 class BaseCPU : public SimObject
 {
+  protected:
+    // CPU's clock period in terms of the number of ticks of curTime.
+    Tick cycleTime;
+
+  public:
+    inline Tick frequency() const { return Clock::Frequency / cycleTime; }
+    inline Tick cycles(int numCycles) const { return cycleTime * numCycles; }
+    inline Tick curCycle() const { return curTick / cycleTime; }
+
 #ifdef FULL_SYSTEM
   protected:
-    Tick frequency;
     uint64_t interrupts[NumInterruptLevels];
     uint64_t intstatus;
 
@@ -67,8 +75,6 @@ class BaseCPU : public SimObject
 
     bool check_interrupts() const { return intstatus != 0; }
     uint64_t intr_status() const { return intstatus; }
-
-    Tick getFreq() const { return frequency; }
 #endif
 
   protected:
@@ -100,7 +106,7 @@ class BaseCPU : public SimObject
         Counter max_insts_all_threads;
         Counter max_loads_any_thread;
         Counter max_loads_all_threads;
-        Tick freq;
+        Tick cycleTime;
         bool functionTrace;
         Tick functionTraceStart;
 #ifdef FULL_SYSTEM
diff --git a/cpu/memtest/memtest.cc b/cpu/memtest/memtest.cc
index 14b119880..86d03e162 100644
--- a/cpu/memtest/memtest.cc
+++ b/cpu/memtest/memtest.cc
@@ -225,7 +225,7 @@ void
 MemTest::tick()
 {
     if (!tickEvent.scheduled())
-        tickEvent.schedule(curTick + 1);
+        tickEvent.schedule(curTick + cycles(1));
 
     if (++noResponseCycles >= 500000) {
         cerr << name() << ": deadlocked at cycle " << curTick << endl;
diff --git a/cpu/memtest/memtest.hh b/cpu/memtest/memtest.hh
index 45b2d24e8..ed25cf374 100644
--- a/cpu/memtest/memtest.hh
+++ b/cpu/memtest/memtest.hh
@@ -60,6 +60,9 @@ class MemTest : public SimObject
 
     // register statistics
     virtual void regStats();
+
+    inline Tick cycles(int numCycles) const { return numCycles; }
+
     // main simulation loop (one cycle)
     void tick();
 
diff --git a/cpu/simple_cpu/simple_cpu.cc b/cpu/simple_cpu/simple_cpu.cc
index 6a95a52c2..719768bf1 100644
--- a/cpu/simple_cpu/simple_cpu.cc
+++ b/cpu/simple_cpu/simple_cpu.cc
@@ -809,7 +809,7 @@ SimpleCPU::tick()
            status() == DcacheMissStall);
 
     if (status() == Running && !tickEvent.scheduled())
-        tickEvent.schedule(curTick + 1);
+        tickEvent.schedule(curTick + cycles(1));
 }
 
 
@@ -834,6 +834,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
     SimObjectParam<Process *> workload;
 #endif // FULL_SYSTEM
 
+    Param<int> cycle_time;
     SimObjectParam<BaseMem *> icache;
     SimObjectParam<BaseMem *> dcache;
 
@@ -865,6 +866,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
     INIT_PARAM(workload, "processes to run"),
 #endif // FULL_SYSTEM
 
+    INIT_PARAM(cycle_time, "cpu cycle time"),
     INIT_PARAM(icache, "L1 instruction cache object"),
     INIT_PARAM(dcache, "L1 data cache object"),
     INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
@@ -890,7 +892,7 @@ CREATE_SIM_OBJECT(SimpleCPU)
     params->max_loads_any_thread = max_loads_any_thread;
     params->max_loads_all_threads = max_loads_all_threads;
     params->deferRegistration = defer_registration;
-    params->freq = ticksPerSecond;
+    params->cycleTime = cycle_time;
     params->functionTrace = function_trace;
     params->functionTraceStart = function_trace_start;
     params->icache_interface = (icache) ? icache->getInterface() : NULL;
diff --git a/cpu/simple_cpu/simple_cpu.hh b/cpu/simple_cpu/simple_cpu.hh
index f245a7bba..2056ff707 100644
--- a/cpu/simple_cpu/simple_cpu.hh
+++ b/cpu/simple_cpu/simple_cpu.hh
@@ -80,12 +80,12 @@ class SimpleCPU : public BaseCPU
     TickEvent tickEvent;
 
     /// Schedule tick event, regardless of its current state.
-    void scheduleTickEvent(int delay)
+    void scheduleTickEvent(int numCycles)
     {
         if (tickEvent.squashed())
-            tickEvent.reschedule(curTick + delay);
+            tickEvent.reschedule(curTick + cycles(numCycles));
         else if (!tickEvent.scheduled())
-            tickEvent.schedule(curTick + delay);
+            tickEvent.schedule(curTick + cycles(numCycles));
     }
 
     /// Unschedule tick event, regardless of its current state.
diff --git a/cpu/trace/trace_cpu.cc b/cpu/trace/trace_cpu.cc
index 1902d0be4..a0e4ef24c 100644
--- a/cpu/trace/trace_cpu.cc
+++ b/cpu/trace/trace_cpu.cc
@@ -108,10 +108,10 @@ TraceCPU::tick()
         if (mainEventQueue.empty()) {
             new SimExitEvent("Finshed Memory Trace");
         } else {
-            tickEvent.schedule(mainEventQueue.nextEventTime() + 1);
+            tickEvent.schedule(mainEventQueue.nextEventTime() + cycles(1));
         }
     } else {
-        tickEvent.schedule(max(curTick + 1, nextCycle));
+        tickEvent.schedule(max(curTick + cycles(1), nextCycle));
     }
 }
 
diff --git a/cpu/trace/trace_cpu.hh b/cpu/trace/trace_cpu.hh
index cdac4bb4f..9b80e325d 100644
--- a/cpu/trace/trace_cpu.hh
+++ b/cpu/trace/trace_cpu.hh
@@ -105,6 +105,8 @@ class TraceCPU : public SimObject
              MemInterface *dcache_interface,
              MemTraceReader *data_trace);
 
+    inline Tick cycles(int numCycles) { return numCycles; }
+
     /**
      * Perform all the accesses for one cycle.
      */