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author | Erik Hallnor <ehallnor@umich.edu> | 2004-02-27 00:45:21 -0500 |
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committer | Erik Hallnor <ehallnor@umich.edu> | 2004-02-27 00:45:21 -0500 |
commit | c3784e37ceba78eee92f46ed92aa2462e238a206 (patch) | |
tree | 6c770a4d8c8feb9f84aef48d0da020ee7478709a /cpu | |
parent | 81c1d76d015490e039172332093c9c876e1f3144 (diff) | |
download | gem5-c3784e37ceba78eee92f46ed92aa2462e238a206.tar.xz |
Initial copy support in the pipeline. Add copypal counting.
arch/alpha/osfpal.cc:
Add a string for copypal.
arch/alpha/osfpal.hh:
Add a code for copypal.
cpu/static_inst.hh:
Add an IsCopy flag.
--HG--
extra : convert_revision : 19e3d90368454806029ad492eace19cd0924fe9f
Diffstat (limited to 'cpu')
-rw-r--r-- | cpu/static_inst.hh | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/cpu/static_inst.hh b/cpu/static_inst.hh index 5f4bcae3d..cdf9aefa0 100644 --- a/cpu/static_inst.hh +++ b/cpu/static_inst.hh @@ -96,6 +96,7 @@ class StaticInstBase : public RefCounted IsStore, ///< Writes to memory. IsInstPrefetch, ///< Instruction-cache prefetch. IsDataPrefetch, ///< Data-cache prefetch. + IsCopy, ///< Fast Cache block copy IsControl, ///< Control transfer instruction. IsDirectControl, ///< PC relative control transfer. @@ -176,6 +177,7 @@ class StaticInstBase : public RefCounted bool isStore() const { return flags[IsStore]; } bool isInstPrefetch() const { return flags[IsInstPrefetch]; } bool isDataPrefetch() const { return flags[IsDataPrefetch]; } + bool isCopy() const { return flags[IsCopy];} bool isInteger() const { return flags[IsInteger]; } bool isFloating() const { return flags[IsFloating]; } |