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authorKorey Sewell <ksewell@umich.edu>2006-03-12 05:58:28 -0500
committerKorey Sewell <ksewell@umich.edu>2006-03-12 05:58:28 -0500
commit57d53f8a9d738b43e0de41a70813e3a6de8d4dfb (patch)
tree2bd45bf1d4a23ca8696b76fbffff3754dd244d4a /cpu
parent18ba0f85486f0dd919064ba2b0ed8c53a7861298 (diff)
parent4d19bbeeebd026b0aab52e381ee77e4141ed9dd1 (diff)
downloadgem5-57d53f8a9d738b43e0de41a70813e3a6de8d4dfb.tar.xz
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem --HG-- extra : convert_revision : b101fa550567d5a9f5de6c2d8c3f67829ae050c1
Diffstat (limited to 'cpu')
-rw-r--r--cpu/cpu_exec_context.cc5
-rw-r--r--cpu/exec_context.hh8
-rw-r--r--cpu/simple/cpu.cc6
-rw-r--r--cpu/simple/cpu.hh5
4 files changed, 20 insertions, 4 deletions
diff --git a/cpu/cpu_exec_context.cc b/cpu/cpu_exec_context.cc
index f840c38dc..2ad9571ce 100644
--- a/cpu/cpu_exec_context.cc
+++ b/cpu/cpu_exec_context.cc
@@ -270,12 +270,12 @@ void
CPUExecContext::copyArchRegs(ExecContext *xc)
{
// First loop through the integer registers.
- for (int i = 0; i < AlphaISA::NumIntRegs; ++i) {
+ for (int i = 0; i < TheISA::NumIntRegs; ++i) {
setIntReg(i, xc->readIntReg(i));
}
// Then loop through the floating point registers.
- for (int i = 0; i < AlphaISA::NumFloatRegs; ++i) {
+ for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
setFloatRegDouble(i, xc->readFloatRegDouble(i));
setFloatRegInt(i, xc->readFloatRegInt(i));
}
@@ -286,5 +286,6 @@ CPUExecContext::copyArchRegs(ExecContext *xc)
// Lastly copy PC/NPC
setPC(xc->readPC());
setNextPC(xc->readNextPC());
+ setNextNPC(xc->readNextNPC());
}
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 225f19b87..3c57ad907 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -189,6 +189,10 @@ class ExecContext
virtual void setNextPC(uint64_t val) = 0;
+ virtual uint64_t readNextNPC() = 0;
+
+ virtual void setNextNPC(uint64_t val) = 0;
+
virtual MiscReg readMiscReg(int misc_reg) = 0;
virtual MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault) = 0;
@@ -362,6 +366,10 @@ class ProxyExecContext : public ExecContext
void setNextPC(uint64_t val) { actualXC->setNextPC(val); }
+ uint64_t readNextNPC() { return actualXC->readNextNPC(); }
+
+ void setNextNPC(uint64_t val) { actualXC->setNextNPC(val); }
+
MiscReg readMiscReg(int misc_reg)
{ return actualXC->readMiscReg(misc_reg); }
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index b5ba6ecc9..44521a542 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -75,9 +75,11 @@
#endif // FULL_SYSTEM
using namespace std;
-//The SimpleCPU does alpha only
-using namespace AlphaISA;
+//The SimpleCPU does alpha only
+//Change this to include arch/isa_traits.hh?
+//using namespace AlphaISA;
+#include "arch/isa_traits.hh"
SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w)
: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w)
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index fbfae950f..21944a49f 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -364,7 +364,12 @@ class SimpleCPU : public BaseCPU
}
uint64_t readPC() { return cpuXC->readPC(); }
+ uint64_t readNextPC() { return cpuXC->readNextPC(); }
+ uint64_t readNextNPC() { return cpuXC->readNextNPC(); }
+
+ void setPC(uint64_t val) { cpuXC->setPC(val); }
void setNextPC(uint64_t val) { cpuXC->setNextPC(val); }
+ void setNextNPC(uint64_t val) { cpuXC->setNextNPC(val); }
MiscReg readMiscReg(int misc_reg)
{