Merge ktlim@zizzer:/bk/m5

into  zamp.eecs.umich.edu:/z/ktlim2/m5-proxyxc

arch/alpha/ev5.cc:
cpu/o3/cpu.hh:
    SCCS merged

--HG--
extra : convert_revision : 38889011ea02005c8fd3a7f3b0be3395223f6166

4 files changed, 6 insertions, 11 deletions

diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index 531f6aa45..0352e9972 100644
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -42,6 +42,8 @@ class AlphaFullCPU : public FullO3CPU<Impl>
   protected:
     typedef TheISA::IntReg IntReg;
     typedef TheISA::MiscReg MiscReg;
+    typedef TheISA::RegFile RegFile;
+    typedef TheISA::MiscRegFile MiscRegFile;
 
   public:
     typedef typename Impl::Params Params;
diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh
index 30ef4bd43..9f1fa24f6 100644
--- a/cpu/o3/alpha_cpu_impl.hh
+++ b/cpu/o3/alpha_cpu_impl.hh
@@ -26,6 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include "arch/alpha/faults.hh"
 #include "base/cprintf.hh"
 #include "base/statistics.hh"
 #include "base/timebuf.hh"
@@ -268,7 +269,7 @@ Fault
 AlphaFullCPU<Impl>::hwrei()
 {
     if (!inPalMode())
-        return new UnimplementedOpcodeFault;
+        return new AlphaISA::UnimplementedOpcodeFault;
 
     this->setNextPC(this->regFile.miscRegs.readReg(AlphaISA::IPR_EXC_ADDR));
 
diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh
index 8f29a25fb..6577e46e4 100644
--- a/cpu/o3/cpu.hh
+++ b/cpu/o3/cpu.hh
@@ -49,11 +49,6 @@
 #include "cpu/o3/cpu_policy.hh"
 #include "sim/process.hh"
 
-#if FULL_SYSTEM
-#include "arch/ev5.hh"
-using namespace EV5;
-#endif
-
 class ExecContext;
 class FunctionalMemory;
 class Process;
@@ -153,11 +148,11 @@ class FullO3CPU : public BaseFullCPU
 
     /** Get instruction asid. */
     int getInstAsid()
-    { return ITB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_ITB_ASN)); }
+    { return regFile.miscRegs.getInstAsid(); }
 
     /** Get data asid. */
     int getDataAsid()
-    { return DTB_ASN_ASN(regFile.miscRegs.readReg(TheISA::IPR_DTB_ASN)); }
+    { return regFile.miscRegs.getDataAsid(); }
 #else
     bool validInstAddr(Addr addr)
     { return thread[0]->validInstAddr(addr); }
diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh
index 03ad2da46..1e6e10f29 100644
--- a/cpu/o3/regfile.hh
+++ b/cpu/o3/regfile.hh
@@ -38,10 +38,8 @@
 #include "cpu/o3/comm.hh"
 
 #if FULL_SYSTEM
-#include "arch/ev5.hh"
 #include "kern/kernel_stats.hh"
 
-using namespace EV5;
 #endif
 
 // This really only depends on the ISA, and not the Impl.  It might be nicer
@@ -237,7 +235,6 @@ class PhysRegFile
   private:
     // This is ISA specifc stuff; remove it eventually once ISAImpl is used
 //    IntReg palregs[NumIntRegs];	// PAL shadow registers
-    InternalProcReg ipr[NumInternalProcRegs]; // internal processor regs
     int intrflag;			// interrupt flag
     bool pal_shadow;		// using pal_shadow registers
 #endif