Change Packet parameters on Port methods from references to pointers.

--HG--
extra : convert_revision : 7193e70304d4cbe1e4cbe16ce0d8527b2754d066

4 files changed, 21 insertions, 21 deletions

diff --git a/cpu/simple/atomic.cc b/cpu/simple/atomic.cc
index 35a69cd4a..c09f16ada 100644
--- a/cpu/simple/atomic.cc
+++ b/cpu/simple/atomic.cc
@@ -78,21 +78,21 @@ AtomicSimpleCPU::init()
 }
 
 bool
-AtomicSimpleCPU::CpuPort::recvTiming(Packet &pkt)
+AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
 {
     panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
     return true;
 }
 
 Tick
-AtomicSimpleCPU::CpuPort::recvAtomic(Packet &pkt)
+AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
 {
     panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
     return curTick;
 }
 
 void
-AtomicSimpleCPU::CpuPort::recvFunctional(Packet &pkt)
+AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
 {
     panic("AtomicSimpleCPU doesn't expect recvFunctional callback!");
 }
@@ -263,7 +263,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
         data_read_pkt->addr = data_read_req->getPaddr();
         data_read_pkt->size = sizeof(T);
 
-        dcache_complete = dcachePort.sendAtomic(*data_read_pkt);
+        dcache_complete = dcachePort.sendAtomic(data_read_pkt);
         dcache_access = true;
 
         assert(data_read_pkt->result == Success);
@@ -345,7 +345,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         data_write_pkt->addr = data_write_req->getPaddr();
         data_write_pkt->size = sizeof(T);
 
-        dcache_complete = dcachePort.sendAtomic(*data_write_pkt);
+        dcache_complete = dcachePort.sendAtomic(data_write_pkt);
         dcache_access = true;
 
         assert(data_write_pkt->result == Success);
@@ -430,7 +430,7 @@ AtomicSimpleCPU::tick()
         Fault fault = setupFetchPacket(ifetch_pkt);
 
         if (fault == NoFault) {
-            Tick icache_complete = icachePort.sendAtomic(*ifetch_pkt);
+            Tick icache_complete = icachePort.sendAtomic(ifetch_pkt);
             // ifetch_req is initialized to read the instruction directly
             // into the CPU object's inst field.
 
diff --git a/cpu/simple/atomic.hh b/cpu/simple/atomic.hh
index 348308c46..d0ba085f0 100644
--- a/cpu/simple/atomic.hh
+++ b/cpu/simple/atomic.hh
@@ -90,11 +90,11 @@ class AtomicSimpleCPU : public BaseSimpleCPU
 
       protected:
 
-        virtual bool recvTiming(Packet &pkt);
+        virtual bool recvTiming(Packet *pkt);
 
-        virtual Tick recvAtomic(Packet &pkt);
+        virtual Tick recvAtomic(Packet *pkt);
 
-        virtual void recvFunctional(Packet &pkt);
+        virtual void recvFunctional(Packet *pkt);
 
         virtual void recvStatusChange(Status status);
 
diff --git a/cpu/simple/timing.cc b/cpu/simple/timing.cc
index a511c3dbb..80d3380a5 100644
--- a/cpu/simple/timing.cc
+++ b/cpu/simple/timing.cc
@@ -60,14 +60,14 @@ TimingSimpleCPU::init()
 }
 
 Tick
-TimingSimpleCPU::CpuPort::recvAtomic(Packet &pkt)
+TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
 {
     panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
     return curTick;
 }
 
 void
-TimingSimpleCPU::CpuPort::recvFunctional(Packet &pkt)
+TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
 {
     panic("TimingSimpleCPU doesn't expect recvFunctional callback!");
 }
@@ -192,7 +192,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
         data_read_pkt->size = sizeof(T);
         data_read_pkt->dest = Packet::Broadcast;
 
-        if (!dcachePort.sendTiming(*data_read_pkt)) {
+        if (!dcachePort.sendTiming(data_read_pkt)) {
             _status = DcacheRetry;
             dcache_pkt = data_read_pkt;
         } else {
@@ -274,7 +274,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         data_write_pkt->addr = data_write_req->getPaddr();
         data_write_pkt->dest = Packet::Broadcast;
 
-        if (!dcachePort.sendTiming(*data_write_pkt)) {
+        if (!dcachePort.sendTiming(data_write_pkt)) {
             _status = DcacheRetry;
             dcache_pkt = data_write_pkt;
         } else {
@@ -354,7 +354,7 @@ TimingSimpleCPU::fetch()
 
     Fault fault = setupFetchPacket(ifetch_pkt);
     if (fault == NoFault) {
-        if (!icachePort.sendTiming(*ifetch_pkt)) {
+        if (!icachePort.sendTiming(ifetch_pkt)) {
             // Need to wait for retry
             _status = IcacheRetry;
         } else {
@@ -406,7 +406,7 @@ TimingSimpleCPU::completeIfetch()
 
 
 bool
-TimingSimpleCPU::IcachePort::recvTiming(Packet &pkt)
+TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
 {
     cpu->completeIfetch();
     return true;
@@ -442,9 +442,9 @@ TimingSimpleCPU::completeDataAccess(Packet *pkt)
 
 
 bool
-TimingSimpleCPU::DcachePort::recvTiming(Packet &pkt)
+TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
 {
-    cpu->completeDataAccess(&pkt);
+    cpu->completeDataAccess(pkt);
     return true;
 }
 
diff --git a/cpu/simple/timing.hh b/cpu/simple/timing.hh
index e1b564c69..83be025d9 100644
--- a/cpu/simple/timing.hh
+++ b/cpu/simple/timing.hh
@@ -77,9 +77,9 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
       protected:
 
-        virtual Tick recvAtomic(Packet &pkt);
+        virtual Tick recvAtomic(Packet *pkt);
 
-        virtual void recvFunctional(Packet &pkt);
+        virtual void recvFunctional(Packet *pkt);
 
         virtual void recvStatusChange(Status status);
 
@@ -98,7 +98,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
       protected:
 
-        virtual bool recvTiming(Packet &pkt);
+        virtual bool recvTiming(Packet *pkt);
 
         virtual Packet *recvRetry();
     };
@@ -113,7 +113,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
       protected:
 
-        virtual bool recvTiming(Packet &pkt);
+        virtual bool recvTiming(Packet *pkt);
 
         virtual Packet *recvRetry();
     };