Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working

after merge from head. Checkpointing may need some work now. Endian-happiness still not complete.

SConscript:
    add all devices back into make file
base/inet.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pktfifo.cc:
dev/pktfifo.hh:
    rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system
configs/test/fs.py:
    add nics to fs.py
cpu/cpu_exec_context.cc:
    remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the
    static virtual ports in the exec context
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
    use new methods for accessing packet data
dev/ide_disk.cc:
    add some more dprintfs
dev/io_device.cc:
    delete packets when we are done with them. Update for new packet methods to access data
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
dev/uart8250.hh:
mem/physical.cc:
mem/port.cc:
    dUpdate for new packet methods to access data
dev/ns_gige.cc:
    Update for new memory system
dev/ns_gige.hh:
python/m5/objects/Ethernet.py:
    update for new memory system
dev/sinic.cc:
dev/sinic.hh:
    Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions
mem/packet.hh:
    Add methods to access data instead of accessing it directly.

--HG--
extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e

3 files changed, 18 insertions, 9 deletions

diff --git a/cpu/cpu_exec_context.cc b/cpu/cpu_exec_context.cc
index 62419adcf..ec1e94561 100644
--- a/cpu/cpu_exec_context.cc
+++ b/cpu/cpu_exec_context.cc
@@ -310,7 +310,7 @@ CPUExecContext::getVirtPort(ExecContext *xc)
 void
 CPUExecContext::delVirtPort(VirtualPort *vp)
 {
-    assert(!vp->nullExecContext());
+//    assert(!vp->nullExecContext());
     delete vp->getPeer();
     delete vp;
 }
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 0f1f9574a..40b506a78 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -172,21 +172,27 @@ SimpleCPU::SimpleCPU(Params *p)
 #if SIMPLE_CPU_MEM_ATOMIC || SIMPLE_CPU_MEM_IMMEDIATE
     ifetch_req = new Request(true);
     ifetch_req->setAsid(0);
+    // @todo fix me and get the real cpu iD!!!
+    ifetch_req->setCpuNum(0);
     ifetch_req->setSize(sizeof(MachInst));
     ifetch_pkt = new Packet;
     ifetch_pkt->cmd = Read;
-    ifetch_pkt->data = (uint8_t *)&inst;
+    ifetch_pkt->dataStatic(&inst);
     ifetch_pkt->req = ifetch_req;
     ifetch_pkt->size = sizeof(MachInst);
 
     data_read_req = new Request(true);
+    // @todo fix me and get the real cpu iD!!!
+    data_read_req->setCpuNum(0);
     data_read_req->setAsid(0);
     data_read_pkt = new Packet;
     data_read_pkt->cmd = Read;
-    data_read_pkt->data = new uint8_t[8];
+    data_read_pkt->dataStatic(&dataReg);
     data_read_pkt->req = data_read_req;
 
     data_write_req = new Request(true);
+    // @todo fix me and get the real cpu iD!!!
+    data_write_req->setCpuNum(0);
     data_write_req->setAsid(0);
     data_write_pkt = new Packet;
     data_write_pkt->cmd = Write;
@@ -474,7 +480,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
 //	Fault fault = xc->read(memReq,data);
         // Not sure what to check for no fault...
         if (data_read_pkt->result == Success) {
-            memcpy(&data, data_read_pkt->data, sizeof(T));
+            data = data_read_pkt->get<T>();
         }
 
         if (traceData) {
@@ -517,7 +523,7 @@ SimpleCPU::read(Addr addr, T &data, unsigned flags)
         // Need to find a way to not duplicate code above.
 
         if (data_read_pkt->result == Success) {
-            memcpy(&data, data_read_pkt->data, sizeof(T));
+            data = data_read_pkt->get<T>();
         }
 
         if (traceData) {
@@ -621,11 +627,11 @@ SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         data_write_pkt = new Packet;
         data_write_pkt->cmd = Write;
         data_write_pkt->req = data_write_req;
-        data_write_pkt->data = new uint8_t[64];
-        memcpy(data_write_pkt->data, &data, sizeof(T));
+        data_write_pkt->allocate();
+        data_write_pkt->set(data);
 #else
         data_write_pkt->reset();
-        data_write_pkt->data = (uint8_t *)&data;
+        data_write_pkt->dataStatic(&data);
 #endif
         data_write_pkt->addr = data_write_req->getPaddr();
         data_write_pkt->size = sizeof(T);
@@ -816,7 +822,7 @@ SimpleCPU::processResponse(Packet &response)
         scheduleTickEvent(1);
 
         // Copy the icache data into the instruction itself.
-        memcpy(&inst, pkt->data, sizeof(inst));
+        inst = pkt->get<MachInst>();
 
         delete pkt;
         break;
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index c3ff5cf3d..3640348a3 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -207,6 +207,9 @@ class SimpleCPU : public BaseCPU
     // current instruction
     MachInst inst;
 
+    // Static data storage
+    TheISA::IntReg dataReg;
+
 #if SIMPLE_CPU_MEM_TIMING
     Packet *retry_pkt;
 #elif SIMPLE_CPU_MEM_ATOMIC || SIMPLE_CPU_MEM_IMMEDIATE