Enable register windows.

arch/alpha/isa_traits.hh:
arch/mips/isa_traits.cc:
    Turned the integer register file into a class instead of a typedef to an array.
arch/alpha/regfile.hh:
    Changed the integer register file into a class instead of a typedef to an array. Also put the parts of the register file, ie the int, float, and misc register files, pc, npc, and nnpc, behind accessor functions. Added a changeContext function, and ContextParam and ContextVal types, so that things like the register window can be changed through call backs.
arch/mips/isa_traits.hh:
    Turned the integer register file into a class instead of a typedef to an array. Also moved a "using namespace" into the namespace definition.
arch/sparc/isa_traits.hh:
    Turned the integer register file into a class instead of a typedef to an array. Also "fixed" the max number of src and dest regs. They may need to be even larger.
arch/sparc/regfile.hh:
    Changed the integer register file into a class instead of a typedef to an array. Also put the parts of the register file, ie the int, float, and misc register files, pc, npc, and nnpc, behind accessor functions. Added a changeContext function, and ContextParam and ContextVal types, so that things like the register window can be changed through call backs. Created setCWP and setAltGlobals functions for the IntRegFile.
cpu/cpu_exec_context.hh:
    Used the accessor functions for the register file, and added a changeRegFileContext function to call back into the RegFile. Used the RegFile clear function rather than memsetting it to 0.
cpu/exec_context.hh:
    Added the changeRegFileContext function.
cpu/exetrace.cc:
    Use the TheISA::NumIntRegs constant, and use readReg now that the integer register file is a class instead of an array.
cpu/exetrace.hh:
    Get the address of the regs object, now that it isn't an array.

--HG--
extra : convert_revision : ea2dd81be1c2e66b3c684af319eb58f8a77fd49c

4 files changed, 43 insertions, 27 deletions

diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh
index 7ceb7f2d8..b023fdcf8 100644
--- a/cpu/cpu_exec_context.hh
+++ b/cpu/cpu_exec_context.hh
@@ -373,103 +373,103 @@ class CPUExecContext
     //
     uint64_t readIntReg(int reg_idx)
     {
-        return regs.intRegFile[reg_idx];
+        return regs.readIntReg(reg_idx);
     }
 
     FloatReg readFloatReg(int reg_idx, int width)
     {
-        return regs.floatRegFile.readReg(reg_idx, width);
+        return regs.readFloatReg(reg_idx, width);
     }
 
     FloatReg readFloatReg(int reg_idx)
     {
-        return regs.floatRegFile.readReg(reg_idx);
+        return regs.readFloatReg(reg_idx);
     }
 
     FloatRegBits readFloatRegBits(int reg_idx, int width)
     {
-        return regs.floatRegFile.readRegBits(reg_idx, width);
+        return regs.readFloatRegBits(reg_idx, width);
     }
 
     FloatRegBits readFloatRegBits(int reg_idx)
     {
-        return regs.floatRegFile.readRegBits(reg_idx);
+        return regs.readFloatRegBits(reg_idx);
     }
 
     void setIntReg(int reg_idx, uint64_t val)
     {
-        regs.intRegFile[reg_idx] = val;
+        regs.setIntReg(reg_idx, val);
     }
 
     void setFloatReg(int reg_idx, FloatReg val, int width)
     {
-        regs.floatRegFile.setReg(reg_idx, val, width);
+        regs.setFloatReg(reg_idx, val, width);
     }
 
     void setFloatReg(int reg_idx, FloatReg val)
     {
-        regs.floatRegFile.setReg(reg_idx, val);
+        regs.setFloatReg(reg_idx, val);
     }
 
     void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
     {
-        regs.floatRegFile.setRegBits(reg_idx, val, width);
+        regs.setFloatRegBits(reg_idx, val, width);
     }
 
     void setFloatRegBits(int reg_idx, FloatRegBits val)
     {
-        regs.floatRegFile.setRegBits(reg_idx, val);
+        regs.setFloatRegBits(reg_idx, val);
     }
 
     uint64_t readPC()
     {
-        return regs.pc;
+        return regs.readPC();
     }
 
     void setPC(uint64_t val)
     {
-        regs.pc = val;
+        regs.setPC(val);
     }
 
     uint64_t readNextPC()
     {
-        return regs.npc;
+        return regs.readNextPC();
     }
 
     void setNextPC(uint64_t val)
     {
-        regs.npc = val;
+        regs.setNextPC(val);
     }
 
     uint64_t readNextNPC()
     {
-        return regs.nnpc;
+        return regs.readNextNPC();
     }
 
     void setNextNPC(uint64_t val)
     {
-        regs.nnpc = val;
+        regs.setNextNPC(val);
     }
 
 
     MiscReg readMiscReg(int misc_reg)
     {
-        return regs.miscRegs.readReg(misc_reg);
+        return regs.readMiscReg(misc_reg);
     }
 
     MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
     {
-        return regs.miscRegs.readRegWithEffect(misc_reg, fault, proxy);
+        return regs.readMiscRegWithEffect(misc_reg, fault, proxy);
     }
 
     Fault setMiscReg(int misc_reg, const MiscReg &val)
     {
-        return regs.miscRegs.setReg(misc_reg, val);
+        return regs.setMiscReg(misc_reg, val);
     }
 
     Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
     {
-        return regs.miscRegs.setRegWithEffect(misc_reg, val, proxy);
+        return regs.setMiscRegWithEffect(misc_reg, val, proxy);
     }
 
     unsigned readStCondFailures() { return storeCondFailures; }
@@ -477,7 +477,7 @@ class CPUExecContext
     void setStCondFailures(unsigned sc_failures)
     { storeCondFailures = sc_failures; }
 
-    void clearArchRegs() { memset(&regs, 0, sizeof(regs)); }
+    void clearArchRegs() { regs.clear(); }
 
 #if FULL_SYSTEM
     int readIntrFlag() { return regs.intrflag; }
@@ -490,13 +490,13 @@ class CPUExecContext
 #if !FULL_SYSTEM
     TheISA::IntReg getSyscallArg(int i)
     {
-        return regs.intRegFile[TheISA::ArgumentReg0 + i];
+        return regs.readIntReg(TheISA::ArgumentReg0 + i);
     }
 
     // used to shift args for indirect syscall
     void setSyscallArg(int i, TheISA::IntReg val)
     {
-        regs.intRegFile[TheISA::ArgumentReg0 + i] = val;
+        regs.setIntReg(TheISA::ArgumentReg0 + i, val);
     }
 
     void setSyscallReturn(SyscallReturn return_value)
@@ -513,6 +513,12 @@ class CPUExecContext
 
     void setFuncExeInst(Counter new_val) { func_exe_inst = new_val; }
 #endif
+
+    void changeRegFileContext(RegFile::ContextParam param,
+            RegFile::ContextVal val)
+    {
+        regs.changeContext(param, val);
+    }
 };
 
 
diff --git a/cpu/exec_context.hh b/cpu/exec_context.hh
index 8f93875a1..2fd49b166 100644
--- a/cpu/exec_context.hh
+++ b/cpu/exec_context.hh
@@ -233,6 +233,9 @@ class ExecContext
 
     virtual void setFuncExeInst(Counter new_val) = 0;
 #endif
+
+    virtual void changeRegFileContext(RegFile::ContextParam param,
+            RegFile::ContextVal val) = 0;
 };
 
 template <class XC>
@@ -422,6 +425,12 @@ class ProxyExecContext : public ExecContext
     void setFuncExeInst(Counter new_val)
     { return actualXC->setFuncExeInst(new_val); }
 #endif
+
+    void changeRegFileContext(RegFile::ContextParam param,
+            RegFile::ContextVal val)
+    {
+        actualXC->changeRegFileContext(param, val);
+    }
 };
 
 #endif
diff --git a/cpu/exetrace.cc b/cpu/exetrace.cc
index 4db72320c..0ed3b43c4 100644
--- a/cpu/exetrace.cc
+++ b/cpu/exetrace.cc
@@ -128,10 +128,11 @@ Trace::InstRecord::dump(ostream &outs)
             outs << " A=0x" << hex << addr;
 
         if (flags[PRINT_INT_REGS] && regs_valid) {
-            for (int i = 0; i < 32;)
+            for (int i = 0; i < TheISA::NumIntRegs;)
                 for (int j = i + 1; i <= j; i++)
-                    ccprintf(outs, "r%02d = %#018x%s", i, iregs->regs[i],
-                             ((i == j) ? "\n" : "    "));
+                    ccprintf(outs, "r%02d = %#018x%s", i,
+                            iregs->regs.readReg(i),
+                            ((i == j) ? "\n" : "    "));
             outs << "\n";
         }
 
diff --git a/cpu/exetrace.hh b/cpu/exetrace.hh
index 67d042ec8..a26cdc517 100644
--- a/cpu/exetrace.hh
+++ b/cpu/exetrace.hh
@@ -163,7 +163,7 @@ InstRecord::setRegs(const IntRegFile &regs)
     if (!iregs)
       iregs = new iRegFile;
 
-    memcpy(&iregs->regs, regs, sizeof(IntRegFile));
+    memcpy(&iregs->regs, &regs, sizeof(IntRegFile));
     regs_valid = true;
 }