Replace Memory with MemObject; no need for two different levels of hierarchy there.

Get rid of addPort().
Change getPort() behavior on PhysicalMemory.

SConscript:
cpu/simple/cpu.hh:
sim/system.cc:
sim/system.hh:
    Replace Memory with MemObject.
cpu/base.hh:
    No need to declare Port here anymore.
cpu/cpu_exec_context.hh:
    Need PageTable definition.
cpu/simple/cpu.cc:
mem/physical.cc:
mem/physical.hh:
    Replace Memory with MemObject.
    Get rid of addPort(); allow getting anonymous ports with getPort().
mem/translating_port.hh:
    Remove unneeded header.
sim/process.cc:
    Replace Memory with MemObject.
    Change how initialization port gets set up to deal with change in
    addPort()/getPort().  Current solution is not ideal but it works.
sim/process.hh:
    Remove unneeded headers and declarations.
    Make LiveProcess::getDesc() abstract instead of panicing if called.
sim/syscall_emul.hh:
    Fix includes.

--HG--
extra : convert_revision : 11d4ffb54230038afcf7219cc46e51f809329a2f

4 files changed, 11 insertions, 12 deletions

diff --git a/cpu/base.hh b/cpu/base.hh
index 0866b49a7..79700c117 100644
--- a/cpu/base.hh
+++ b/cpu/base.hh
@@ -42,7 +42,6 @@ class System;
 namespace Kernel { class Statistics; }
 class BranchPred;
 class ExecContext;
-class Port;
 
 class BaseCPU : public SimObject
 {
diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh
index 509583d65..9268f6f3d 100644
--- a/cpu/cpu_exec_context.hh
+++ b/cpu/cpu_exec_context.hh
@@ -53,6 +53,7 @@ class MemoryController;
 #else // !FULL_SYSTEM
 
 #include "sim/process.hh"
+#include "mem/page_table.hh"
 class TranslatingPort;
 
 #endif // FULL_SYSTEM
diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 6e8764709..b99ace598 100644
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -71,7 +71,7 @@
 #include "arch/stacktrace.hh"
 #include "arch/vtophys.hh"
 #else // !FULL_SYSTEM
-#include "mem/memory.hh"
+#include "mem/mem_object.hh"
 #endif // FULL_SYSTEM
 
 using namespace std;
@@ -152,13 +152,13 @@ SimpleCPU::SimpleCPU(Params *p)
     _status = Idle;
 
     //Create Memory Ports (conect them up)
-    p->mem->addPort("DCACHE");
-    dcachePort.setPeer(p->mem->getPort("DCACHE"));
-    (p->mem->getPort("DCACHE"))->setPeer(&dcachePort);
+    Port *mem_dport = p->mem->getPort();
+    dcachePort.setPeer(mem_dport);
+    mem_dport->setPeer(&dcachePort);
 
-    p->mem->addPort("ICACHE");
-    icachePort.setPeer(p->mem->getPort("ICACHE"));
-    (p->mem->getPort("ICACHE"))->setPeer(&icachePort);
+    Port *mem_iport = p->mem->getPort();
+    icachePort.setPeer(mem_iport);
+    mem_iport->setPeer(&icachePort);
 
 #if FULL_SYSTEM
     cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
@@ -1128,7 +1128,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
     Param<int> cpu_id;
     Param<Tick> profile;
 #else
-    SimObjectParam<Memory *> mem;
+    SimObjectParam<MemObject *> mem;
     SimObjectParam<Process *> workload;
 #endif // FULL_SYSTEM
 
diff --git a/cpu/simple/cpu.hh b/cpu/simple/cpu.hh
index 21944a49f..ed464c605 100644
--- a/cpu/simple/cpu.hh
+++ b/cpu/simple/cpu.hh
@@ -46,7 +46,7 @@
 class Processor;
 class AlphaITB;
 class AlphaDTB;
-class Memory;
+class MemObject;
 
 class RemoteGDB;
 class GDBListener;
@@ -58,7 +58,6 @@ class Process;
 #endif // FULL_SYSTEM
 
 class ExecContext;
-class MemInterface;
 class Checkpoint;
 
 namespace Trace {
@@ -180,7 +179,7 @@ class SimpleCPU : public BaseCPU
         AlphaITB *itb;
         AlphaDTB *dtb;
 #else
-        Memory *mem;
+        MemObject *mem;
         Process *process;
 #endif
     };