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authorGabe Black <gblack@eecs.umich.edu>2006-02-24 18:45:28 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-02-24 18:45:28 -0500
commite66f521d5be35683fc9460b2c4d6b7fb35fad940 (patch)
treee290f340b7c1d5d999ee61ca3a4db008ecdc7517 /dev/alpha_console.cc
parent802fd04f640b34d713f7ef75142e51d3d82559b9 (diff)
parent7a37037358ae5800d0f6a40130929669d836fe70 (diff)
downloadgem5-e66f521d5be35683fc9460b2c4d6b7fb35fad940.tar.xz
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch SConscript: arch/alpha/ev5.cc: dev/alpha_console.cc: Hand merged --HG-- extra : convert_revision : 318a671e6803400d3ed086a90e70d6790e4f6b19
Diffstat (limited to 'dev/alpha_console.cc')
-rw-r--r--dev/alpha_console.cc46
1 files changed, 18 insertions, 28 deletions
diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc
index 87d8c4e93..85134b435 100644
--- a/dev/alpha_console.cc
+++ b/dev/alpha_console.cc
@@ -81,9 +81,7 @@ AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
alphaAccess->diskOperation = 0;
alphaAccess->outputChar = 0;
alphaAccess->inputChar = 0;
- alphaAccess->bootStrapImpure = 0;
- alphaAccess->bootStrapCPU = 0;
- alphaAccess->align2 = 0;
+ bzero(alphaAccess->cpuStack, sizeof(alphaAccess->cpuStack));
system->setAlphaAccess(addr);
}
@@ -123,9 +121,6 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
case offsetof(AlphaAccess, numCPUs):
*(uint32_t*)data = alphaAccess->numCPUs;
break;
- case offsetof(AlphaAccess, bootStrapCPU):
- *(uint32_t*)data = alphaAccess->bootStrapCPU;
- break;
case offsetof(AlphaAccess, intrClockFrequency):
*(uint32_t*)data = alphaAccess->intrClockFrequency;
break;
@@ -176,11 +171,14 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
case offsetof(AlphaAccess, outputChar):
*(uint64_t*)data = alphaAccess->outputChar;
break;
- case offsetof(AlphaAccess, bootStrapImpure):
- *(uint64_t*)data = alphaAccess->bootStrapImpure;
- break;
default:
- panic("Unknown 64bit access, %#x\n", daddr);
+ int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
+ sizeof(alphaAccess->cpuStack[0]);
+
+ if (cpunum >= 0 && cpunum < 64)
+ *(uint64_t*)data = alphaAccess->cpuStack[cpunum];
+ else
+ panic("Unknown 64bit access, %#x\n", daddr);
}
break;
default:
@@ -240,24 +238,18 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
console->out((char)(val & 0xff));
break;
- case offsetof(AlphaAccess, bootStrapImpure):
- alphaAccess->bootStrapImpure = val;
- break;
-
- case offsetof(AlphaAccess, bootStrapCPU):
- warn("%d: Trying to launch another CPU!", curTick);
- assert(val > 0 && "Must not access primary cpu");
-
- other_xc = req->xc->system->execContexts[val];
- other_xc->regs.intRegFile[16] = val;
- other_xc->regs.ipr[TheISA::IPR_PALtemp16] = val;
- other_xc->regs.intRegFile[0] = val;
- other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure;
other_xc->activate(); //Start the cpu
break;
default:
- return new MachineCheckFault;
+ int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
+ sizeof(alphaAccess->cpuStack[0]);
+ warn("%d: Trying to launch CPU number %d!", curTick, cpunum);
+ assert(val > 0 && "Must not access primary cpu");
+ if (cpunum >= 0 && cpunum < 64)
+ alphaAccess->cpuStack[cpunum] = val;
+ else
+ panic("Unknown 64bit access, %#x\n", daddr);
}
return NoFault;
@@ -288,8 +280,7 @@ AlphaConsole::Access::serialize(ostream &os)
SERIALIZE_SCALAR(diskOperation);
SERIALIZE_SCALAR(outputChar);
SERIALIZE_SCALAR(inputChar);
- SERIALIZE_SCALAR(bootStrapImpure);
- SERIALIZE_SCALAR(bootStrapCPU);
+ SERIALIZE_ARRAY(cpuStack,64);
}
void
@@ -311,8 +302,7 @@ AlphaConsole::Access::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_SCALAR(diskOperation);
UNSERIALIZE_SCALAR(outputChar);
UNSERIALIZE_SCALAR(inputChar);
- UNSERIALIZE_SCALAR(bootStrapImpure);
- UNSERIALIZE_SCALAR(bootStrapCPU);
+ UNSERIALIZE_ARRAY(cpuStack, 64);
}
void