Add support for all devices to get requests from a timing memory bus.

In the future, this can be used for actual data, but for now, it's
so that devices can respond to timing accesses properly.  This way,
an uncached access on a bus further away will take longer to respond.

dev/alpha_console.cc:
dev/alpha_console.hh:
    suport the separate IO bus

--HG--
extra : convert_revision : ececb70f5febfd00231f6e406f93b2a79be01261

1 files changed, 7 insertions, 3 deletions

diff --git a/dev/alpha_console.hh b/dev/alpha_console.hh
index 54a2af6d5..b617b64e7 100644
--- a/dev/alpha_console.hh
+++ b/dev/alpha_console.hh
@@ -35,7 +35,7 @@
 
 #include "base/range.hh"
 #include "dev/alpha_access.h"
-#include "mem/functional_mem/functional_memory.hh"
+#include "dev/io_device.hh"
 #include "sim/host.hh"
 
 class BaseCPU;
@@ -69,7 +69,7 @@ class SimpleDisk;
  * primarily used doing boot before the kernel has loaded its device
  * drivers.
  */
-class AlphaConsole : public FunctionalMemory
+class AlphaConsole : public PioDevice
 {
   protected:
     union {
@@ -90,7 +90,8 @@ class AlphaConsole : public FunctionalMemory
     /** Standard Constructor */
     AlphaConsole(const std::string &name, SimConsole *cons, SimpleDisk *d,
                  System *system, BaseCPU *cpu, TlaserClock *clock,
-                 int num_cpus, MemoryController *mmu, Addr addr);
+                 int num_cpus, MemoryController *mmu, Addr addr,
+                 HierParams *hier, Bus *bus);
 
     /**
      * memory mapped reads and writes
@@ -103,6 +104,9 @@ class AlphaConsole : public FunctionalMemory
      */
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+  public:
+    Tick cacheAccess(MemReqPtr &req);
 };
 
 #endif // __ALPHA_CONSOLE_HH__