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authorNathan Binkert <binkertn@umich.edu>2004-07-12 22:58:22 -0400
committerNathan Binkert <binkertn@umich.edu>2004-07-12 22:58:22 -0400
commit13f8dc981fc898e6e200689d305b39f0718f8c83 (patch)
treee75ced9115aef60e6c173e08633e19ba92b62569 /dev/baddev.cc
parentc2e5caf3606b85b6f45cde53b8021692ef01710e (diff)
downloadgem5-13f8dc981fc898e6e200689d305b39f0718f8c83.tar.xz
make the cache access latency a parameter that is based on bus
ticks for the most commonly accessed devices. dev/baddev.cc: Get rid of the constant cache access latency. For unimportant devices, don't add any latency. dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ns_gige.cc: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/uart.cc: dev/uart.hh: make the cache access latency a parameter that is based on bus ticks. dev/io_device.cc: dev/io_device.hh: add an io latency variable dev/ns_gige.hh: this moved to io_device.hh --HG-- extra : convert_revision : 4883130feeaef48abee492eddf0b8eb40eb94789
Diffstat (limited to 'dev/baddev.cc')
-rw-r--r--dev/baddev.cc5
1 files changed, 3 insertions, 2 deletions
diff --git a/dev/baddev.cc b/dev/baddev.cc
index 8b552e989..7c563e80a 100644
--- a/dev/baddev.cc
+++ b/dev/baddev.cc
@@ -78,7 +78,7 @@ BadDevice::write(MemReqPtr &req, const uint8_t *data)
Tick
BadDevice::cacheAccess(MemReqPtr &req)
{
- return curTick + 1000;
+ return curTick;
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
@@ -103,7 +103,8 @@ END_INIT_SIM_OBJECT_PARAMS(BadDevice)
CREATE_SIM_OBJECT(BadDevice)
{
- return new BadDevice(getInstanceName(), addr, mmu, hier, io_bus, devicename);
+ return new BadDevice(getInstanceName(), addr, mmu, hier, io_bus,
+ devicename);
}
REGISTER_SIM_OBJECT("BadDevice", BadDevice)