Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working

after merge from head. Checkpointing may need some work now. Endian-happiness still not complete.

SConscript:
    add all devices back into make file
base/inet.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pktfifo.cc:
dev/pktfifo.hh:
    rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system
configs/test/fs.py:
    add nics to fs.py
cpu/cpu_exec_context.cc:
    remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the
    static virtual ports in the exec context
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
    use new methods for accessing packet data
dev/ide_disk.cc:
    add some more dprintfs
dev/io_device.cc:
    delete packets when we are done with them. Update for new packet methods to access data
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
dev/uart8250.hh:
mem/physical.cc:
mem/port.cc:
    dUpdate for new packet methods to access data
dev/ns_gige.cc:
    Update for new memory system
dev/ns_gige.hh:
python/m5/objects/Ethernet.py:
    update for new memory system
dev/sinic.cc:
dev/sinic.hh:
    Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions
mem/packet.hh:
    Add methods to access data instead of accessing it directly.

--HG--
extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e

1 files changed, 4 insertions, 4 deletions

diff --git a/dev/etherlink.hh b/dev/etherlink.hh
index 305007d9e..570444e1b 100644
--- a/dev/etherlink.hh
+++ b/dev/etherlink.hh
@@ -73,14 +73,14 @@ class EtherLink : public SimObject
         /*
          * Transfer is complete
          */
-        PacketPtr packet;
+        EthPacketPtr packet;
         void txDone();
         typedef EventWrapper<Link, &Link::txDone> DoneEvent;
         friend void DoneEvent::process();
         DoneEvent doneEvent;
 
         friend class LinkDelayEvent;
-        void txComplete(PacketPtr packet);
+        void txComplete(EthPacketPtr packet);
 
       public:
         Link(const std::string &name, EtherLink *p, int num,
@@ -90,7 +90,7 @@ class EtherLink : public SimObject
         const std::string name() const { return objName; }
 
         bool busy() const { return (bool)packet; }
-        bool transmit(PacketPtr packet);
+        bool transmit(EthPacketPtr packet);
 
         void setTxInt(Interface *i) { assert(!txint); txint = i; }
         void setRxInt(Interface *i) { assert(!rxint); rxint = i; }
@@ -110,7 +110,7 @@ class EtherLink : public SimObject
 
       public:
         Interface(const std::string &name, Link *txlink, Link *rxlink);
-        bool recvPacket(PacketPtr packet) { return txlink->transmit(packet); }
+        bool recvPacket(EthPacketPtr packet) { return txlink->transmit(packet); }
         void sendDone() { peer->sendDone(); }
     };