diff options
| author | Andrew Schultz <alschult@umich.edu> | 2004-05-19 15:58:24 -0400 |
|---|---|---|
| committer | Andrew Schultz <alschult@umich.edu> | 2004-05-19 15:58:24 -0400 |
| commit | f5c7b1358cf0b27c27c10eae42e09949613e24a9 (patch) | |
| tree | 1b969afae3bd82ee6e126ce94403bdf1112ff1c4 /dev/ide_ctrl.cc | |
| parent | 675b849b50083c1bcde52c806fc5e03702142371 (diff) | |
| download | gem5-f5c7b1358cf0b27c27c10eae42e09949613e24a9.tar.xz | |
Remove the uncacheable bit 39 check (needs to be merged in with head tree
if Tru64 is to continue to be supported on Turbolaser) and fixed
translation of physical addresses by clearing PA<42:35> when the real
uncachable bit (43) is set
arch/alpha/ev5.hh:
Change to support 256 ASNs and seperate VA_SPACE checks for EV5 and EV6
also add support proper translation of uncacheable physical addresses
dev/ide_ctrl.cc:
Fix to work with real address translation
--HG--
extra : convert_revision : aa3d1c284b8271d4763a8da2509c91bbcf83189a
Diffstat (limited to 'dev/ide_ctrl.cc')
| -rw-r--r-- | dev/ide_ctrl.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc index a21cf12d7..f78a8e1ef 100644 --- a/dev/ide_ctrl.cc +++ b/dev/ide_ctrl.cc @@ -357,7 +357,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data) pioInterface->addAddrRange(pri_cmd_addr, pri_cmd_addr + pri_cmd_size - 1); - pri_cmd_addr = ((pri_cmd_addr | 0xf0000000000ULL) & PA_IMPL_MASK); + pri_cmd_addr = pri_cmd_addr & PA_UNCACHED_MASK; break; case PCI0_BASE_ADDR1: @@ -366,7 +366,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data) pioInterface->addAddrRange(pri_ctrl_addr, pri_ctrl_addr + pri_ctrl_size - 1); - pri_ctrl_addr = ((pri_ctrl_addr | 0xf0000000000ULL) & PA_IMPL_MASK); + pri_ctrl_addr = pri_ctrl_addr & PA_UNCACHED_MASK; break; case PCI0_BASE_ADDR2: @@ -375,7 +375,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data) pioInterface->addAddrRange(sec_cmd_addr, sec_cmd_addr + sec_cmd_size - 1); - sec_cmd_addr = ((sec_cmd_addr | 0xf0000000000ULL) & PA_IMPL_MASK); + sec_cmd_addr = sec_cmd_addr & PA_UNCACHED_MASK; break; case PCI0_BASE_ADDR3: @@ -384,7 +384,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data) pioInterface->addAddrRange(sec_ctrl_addr, sec_ctrl_addr + sec_ctrl_size - 1); - sec_ctrl_addr = ((sec_ctrl_addr | 0xf0000000000ULL) & PA_IMPL_MASK); + sec_ctrl_addr = sec_ctrl_addr & PA_UNCACHED_MASK; break; case PCI0_BASE_ADDR4: @@ -392,7 +392,7 @@ IdeController::WriteConfig(int offset, int size, uint32_t data) if (pioInterface) pioInterface->addAddrRange(bmi_addr, bmi_addr + bmi_size - 1); - bmi_addr = ((bmi_addr | 0xf0000000000ULL) & PA_IMPL_MASK); + bmi_addr = bmi_addr & PA_UNCACHED_MASK; break; } } |