diff options
author | Nathan Binkert <binkertn@umich.edu> | 2004-07-12 22:58:22 -0400 |
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committer | Nathan Binkert <binkertn@umich.edu> | 2004-07-12 22:58:22 -0400 |
commit | 13f8dc981fc898e6e200689d305b39f0718f8c83 (patch) | |
tree | e75ced9115aef60e6c173e08633e19ba92b62569 /dev/ide_ctrl.cc | |
parent | c2e5caf3606b85b6f45cde53b8021692ef01710e (diff) | |
download | gem5-13f8dc981fc898e6e200689d305b39f0718f8c83.tar.xz |
make the cache access latency a parameter that is based on bus
ticks for the most commonly accessed devices.
dev/baddev.cc:
Get rid of the constant cache access latency.
For unimportant devices, don't add any latency.
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart.cc:
dev/uart.hh:
make the cache access latency a parameter that is based on bus
ticks.
dev/io_device.cc:
dev/io_device.hh:
add an io latency variable
dev/ns_gige.hh:
this moved to io_device.hh
--HG--
extra : convert_revision : 4883130feeaef48abee492eddf0b8eb40eb94789
Diffstat (limited to 'dev/ide_ctrl.cc')
-rw-r--r-- | dev/ide_ctrl.cc | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc index 4805570d2..e40248461 100644 --- a/dev/ide_ctrl.cc +++ b/dev/ide_ctrl.cc @@ -60,7 +60,7 @@ IdeController::IdeController(const string &name, IntrControl *ic, MemoryController *mmu, PciConfigAll *cf, PciConfigData *cd, Tsunami *t, uint32_t bus_num, uint32_t dev_num, uint32_t func_num, - Bus *host_bus, HierParams *hier) + Bus *host_bus, Tick pio_latency, HierParams *hier) : PciDev(name, mmu, cf, cd, bus_num, dev_num, func_num), tsunami(t) { // put back pointer into Tsunami @@ -105,6 +105,7 @@ IdeController::IdeController(const string &name, IntrControl *ic, dmaInterface = new DMAInterface<Bus>(name + ".dma", host_bus, host_bus, 1); + pioLatency = pio_latency * host_bus->clockRatio; } // setup the disks attached to controller @@ -261,7 +262,7 @@ Tick IdeController::cacheAccess(MemReqPtr &req) { // @todo Add more accurate timing to cache access - return curTick + 1000; + return curTick + pioLatency; } //// @@ -700,6 +701,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController) Param<uint32_t> pci_dev; Param<uint32_t> pci_func; SimObjectParam<Bus *> io_bus; + Param<Tick> pio_latency; SimObjectParam<HierParams *> hier; END_DECLARE_SIM_OBJECT_PARAMS(IdeController) @@ -716,6 +718,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController) INIT_PARAM(pci_dev, "PCI device number"), INIT_PARAM(pci_func, "PCI function code"), INIT_PARAM_DFLT(io_bus, "Host bus to attach to", NULL), + INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams) END_INIT_SIM_OBJECT_PARAMS(IdeController) @@ -724,7 +727,7 @@ CREATE_SIM_OBJECT(IdeController) { return new IdeController(getInstanceName(), intr_ctrl, disks, mmu, configspace, configdata, tsunami, pci_bus, - pci_dev, pci_func, io_bus, hier); + pci_dev, pci_func, io_bus, pio_latency, hier); } REGISTER_SIM_OBJECT("IdeController", IdeController) |