Changes for getting FreeBSD to run.

SConscript:
    Added more files to compile: dev/pcifake.cc, dev/isa_fake.cc, kern/freebsd/freebsd_system.cc, kern/freebsd/freebsd_events.cc.
arch/alpha/isa_traits.hh:
    Added constant for argument register 2 as it is needed by FreebsdSystem::doCalibrateClocks().
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
    Replaced htoa()s with gtoh() and htog().
cpu/o3/fetch_impl.hh:
cpu/simple/cpu.cc:
    Replaced htoa() with gtoh().
dev/disk_image.cc:
    Replaced htoa()s with letoh()s.
dev/ide_ctrl.cc:
    Got rid of magic numbers.
    Added IdeChannel and IdeRegType type names where necessary.
dev/ide_ctrl.hh:
    Got rid of unnecessary macros.
    Changed RegType_t to IdeRegType.
    Changed bmi_regs to allow accessing registers by name instead of just by array index.
    Added IdeChannel enum type to use in place of bool variables which were used to specify IDE channel.
dev/ide_disk.cc:
    Rewrote IdeDisk::read and IdeDisk::write functions to specify registers by name instead of indexing through an array.
dev/ide_disk.hh:
    Updated command register struct.
dev/ns_gige.cc:
dev/ns_gige.hh:
    Made ReadConfig and WriteConfig begin with a lower-case letter.
    writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pciconfigall.cc:
    writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pcidev.cc:
    Cleaned up readConfig() and writeConfig() functions.
dev/pcidev.hh:
    Added macros to make code that works with the BARs (base adress registers) more readable. writeConfig() now takes a pointer to data.
dev/pcireg.h:
    Changed PCIConfig struct to make accessing elements more straight forward. Removed type 1 (for PCI-to-PCI bridges) PCI configuration space struct since it is not used.
dev/rtcreg.h:
    Added macros for bit fields in RTC status registers A & B.
dev/sinic.cc:
    Function name change: WriteConfig --> writeConfig.
    writeConfig() now takes a pointer to data instead of a copy of data.
    The accessing of elements of PCIConfig structure is updated.
dev/sinic.hh:
    Function name change: WriteConfig --> writeConfig.
    writeConfig() now takes a pointer to data instead of a copy of data.
dev/tsunami_io.cc:
    Added implementation of new RTC and PIT classes.
dev/tsunami_io.hh:
    Added classes for RTC and PIT modules.
dev/tsunamireg.h:
    Added macros for DMA ports used by Tsunami-Tru64.
dev/uart8250.cc:
    Got rid of a magic number.
    Transmit (Tx) interrupts should clear upon a read of the Interrupt ID register.
dev/uart8250.hh:
    Added comments and macros dealing with the UART Interrupt ID register.
kern/linux/linux_system.cc:
    Replaced htoa() with htog().
python/m5/objects/Pci.py:
    PciFake is a python class for Pci Devices that do nothing.
python/m5/objects/Tsunami.py:
    TsunamiFake was renamed as IsaFake.
sim/system.cc:
    Replaced htoa()s with htog()s.
dev/isa_fake.cc:
    New BitKeeper file ``dev/isa_fake.cc''
    TsunamiFake was renamed as IsaFake.
dev/isa_fake.hh:
    New BitKeeper file ``dev/isa_fake.hh''
    TsunmaiFake was renamed as IsaFake.
dev/pitreg.h:
    New BitKeeper file ``dev/pitreg.h''
    Useful macros for working with PIT (Periodic Interval Timer) registers.

--HG--
extra : convert_revision : 33f3a8a1034af4f6c71b32dd743e371c8613e780

1 files changed, 61 insertions, 21 deletions

diff --git a/dev/ide_ctrl.hh b/dev/ide_ctrl.hh
index 4b54c3d57..d50dbbeb1 100644
--- a/dev/ide_ctrl.hh
+++ b/dev/ide_ctrl.hh
@@ -63,22 +63,19 @@
 #define IDE_FEATURE_OFFSET      IDE_ERROR_OFFSET
 #define IDE_COMMAND_OFFSET      IDE_STATUS_OFFSET
 
+// IDE Timing Register bit fields
+#define IDETIM_DECODE_EN 0x8000
+
 // PCI device specific register byte offsets
-#define PCI_IDE_TIMING    0x40
-#define PCI_SLAVE_TIMING  0x44
-#define PCI_UDMA33_CTRL   0x48
-#define PCI_UDMA33_TIMING 0x4a
-
-#define IDETIM  (0)
-#define SIDETIM (4)
-#define UDMACTL (5)
-#define UDMATIM (6)
-
-typedef enum RegType {
-    COMMAND_BLOCK = 0,
+#define IDE_CTRL_CONF_START 0x40
+#define IDE_CTRL_CONF_END ((IDE_CTRL_CONF_START) + sizeof(config_regs))
+
+
+enum IdeRegType {
+    COMMAND_BLOCK,
     CONTROL_BLOCK,
     BMI_BLOCK
-} RegType_t;
+};
 
 class BaseInterface;
 class Bus;
@@ -97,6 +94,11 @@ class IdeController : public PciDev
 {
     friend class IdeDisk;
 
+    enum IdeChannel {
+        PRIMARY = 0,
+        SECONDARY = 1
+    };
+
   private:
     /** Primary command block registers */
     Addr pri_cmd_addr;
@@ -116,11 +118,49 @@ class IdeController : public PciDev
 
   private:
     /** Registers used for bus master interface */
-    uint8_t bmi_regs[16];
+    union {
+        uint8_t data[16];
+
+        struct {
+            uint8_t bmic0;
+            uint8_t reserved_0;
+            uint8_t bmis0;
+            uint8_t reserved_1;
+            uint32_t bmidtp0;
+            uint8_t bmic1;
+            uint8_t reserved_2;
+            uint8_t bmis1;
+            uint8_t reserved_3;
+            uint32_t bmidtp1;
+        };
+
+        struct {
+            uint8_t bmic;
+            uint8_t reserved_4;
+            uint8_t bmis;
+            uint8_t reserved_5;
+            uint32_t bmidtp;
+        } chan[2];
+
+    } bmi_regs;
     /** Shadows of the device select bit */
     uint8_t dev[2];
-    /** Registers used in PCI configuration */
-    uint8_t pci_regs[8];
+    /** Registers used in device specific PCI configuration */
+    union {
+        uint8_t data[22];
+
+        struct {
+            uint16_t idetim0;
+            uint16_t idetim1;
+            uint8_t sidetim;
+            uint8_t reserved_0[3];
+            uint8_t udmactl;
+            uint8_t reserved_1;
+            uint16_t udmatim;
+            uint8_t reserved_2[8];
+            uint16_t ideconfig;
+        };
+    } config_regs;
 
     // Internal management variables
     bool io_enabled;
@@ -133,11 +173,11 @@ class IdeController : public PciDev
 
   private:
     /** Parse the access address to pass on to device */
-    void parseAddr(const Addr &addr, Addr &offset, bool &primary,
-                   RegType_t &type);
+    void parseAddr(const Addr &addr, Addr &offset, IdeChannel &channel,
+                   IdeRegType &reg_type);
 
     /** Select the disk based on the channel and device bit */
-    int getDisk(bool primary);
+    int getDisk(IdeChannel channel);
 
     /** Select the disk based on a pointer */
     int getDisk(IdeDisk *diskPtr);
@@ -161,8 +201,8 @@ class IdeController : public PciDev
     IdeController(Params *p);
     ~IdeController();
 
-    virtual void WriteConfig(int offset, int size, uint32_t data);
-    virtual void ReadConfig(int offset, int size, uint8_t *data);
+    virtual void writeConfig(int offset, int size, const uint8_t *data);
+    virtual void readConfig(int offset, int size, uint8_t *data);
 
     void setDmaComplete(IdeDisk *disk);