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author | Ali Saidi <saidi@eecs.umich.edu> | 2004-06-10 13:30:58 -0400 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2004-06-10 13:30:58 -0400 |
commit | 02f69b94c540a6b116c1a71a97f16facd21a5c44 (patch) | |
tree | 7141d773d09c16f15b6785d5f6420129f7279c5f /dev/ide_ctrl.hh | |
parent | a20f44979afd2a77d8b699534a4029d1e35464de (diff) | |
download | gem5-02f69b94c540a6b116c1a71a97f16facd21a5c44.tar.xz |
Fixes for detailed boot, made cttz and ctlz instructions more compact,
and started cleaning up config files.
arch/alpha/isa_desc:
Made implementation of cttz and ctlz more compact
base/remote_gdb.cc:
Added comment about PALcode debugger accesses
dev/baddev.cc:
dev/baddev.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
Cleaned up includes and changed device from FunctionalMemory to
PioDevice for detailed boot
dev/ns_gige.cc:
The ethernet dev uses two BARs, and the first bars size was being set
incorrectly.
dev/tsunamireg.h:
I don't know why we were using the superpage as the PCI memory addr.
Changed and works correctly with detailed boot.
--HG--
extra : convert_revision : b535e76612cb90b544305dc1aa8c5e0e774564bd
Diffstat (limited to 'dev/ide_ctrl.hh')
-rw-r--r-- | dev/ide_ctrl.hh | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/dev/ide_ctrl.hh b/dev/ide_ctrl.hh index cfdef8e3a..9418c8895 100644 --- a/dev/ide_ctrl.hh +++ b/dev/ide_ctrl.hh @@ -199,12 +199,6 @@ class IdeController : public PciDev virtual Fault write(MemReqPtr &req, const uint8_t *data); /** - * Cache access timing specific to device - * @param req Memory request - */ - Tick cacheAccess(MemReqPtr &req); - - /** * Serialize this object to the given output stream. * @param os The stream to serialize to. */ @@ -217,5 +211,11 @@ class IdeController : public PciDev */ virtual void unserialize(Checkpoint *cp, const std::string §ion); + /** + * Return how long this access will take. + * @param req the memory request to calcuate + * @return Tick when the request is done + */ + Tick cacheAccess(MemReqPtr &req); }; #endif // __IDE_CTRL_HH_ |