Checkin of latest IDE and some separation between platforms (Tsunami and

Turbolaser)

base/range.hh:
    Change semantics of range to be inclusive of the end value, may need to
    check other users of range to make sure they are semantically correct.
    This was needed for access of last byte in range of address on IDE and
    makes sense for case of range from 0 to all f
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
    Whole mess of changes.. at current state simulator will boot and read
    partition table and then have a bunch of errors and panic
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/platform.hh:
    Changes to work with platform separation
dev/tsunami.cc:
dev/tsunami.hh:
    Change to work with platform separation

--HG--
extra : convert_revision : e1de22b54df7fdcf391efc2a8555ada93f46beab

1 files changed, 239 insertions, 7 deletions

diff --git a/dev/ide_disk.hh b/dev/ide_disk.hh
index 29ddd4be7..9bb695bee 100644
--- a/dev/ide_disk.hh
+++ b/dev/ide_disk.hh
@@ -33,34 +33,203 @@
 #ifndef __IDE_DISK_HH__
 #define __IDE_DISK_HH__
 
+#include "dev/ide.hh"
+#include "dev/disk_image.hh"
 #include "dev/io_device.hh"
+#include "sim/eventq.hh"
 
-class DiskImage;
+#define DMA_BACKOFF_PERIOD 200
+
+#define MAX_DMA_SIZE (16384)
+#define MAX_MULTSECT (32)
+
+#define PRD_BASE_MASK  0xfffffffe
+#define PRD_COUNT_MASK 0xfffe
+#define PRD_EOT_MASK   0x8000
+
+typedef struct PrdEntry {
+    uint32_t baseAddr;
+    uint16_t byteCount;
+    uint16_t endOfTable;
+} PrdEntry_t;
+
+class PrdTableEntry {
+  public:
+    PrdEntry_t entry;
+
+    uint32_t getBaseAddr()
+    {
+        return (entry.baseAddr & PRD_BASE_MASK);
+    }
+
+    uint16_t getByteCount()
+    {
+        return ((entry.byteCount == 0) ? MAX_DMA_SIZE :
+                (entry.byteCount & PRD_COUNT_MASK));
+    }
+
+    uint16_t getEOT()
+    {
+        return (entry.endOfTable & PRD_EOT_MASK);
+    }
+};
+
+#define DATA_OFFSET     (0)
+#define ERROR_OFFSET    (1)
+#define FEATURES_OFFSET (1)
+#define NSECTOR_OFFSET  (2)
+#define SECTOR_OFFSET   (3)
+#define LCYL_OFFSET     (4)
+#define HCYL_OFFSET     (5)
+#define SELECT_OFFSET   (6)
+#define STATUS_OFFSET   (7)
+#define COMMAND_OFFSET  (7)
+
+#define CONTROL_OFFSET  (2)
+#define ALTSTAT_OFFSET  (2)
+
+#define SELECT_DEV_BIT  0x10
+#define CONTROL_RST_BIT 0x04
+#define CONTROL_IEN_BIT 0x02
+#define STATUS_BSY_BIT  0x80
+#define STATUS_DRDY_BIT 0x40
+#define STATUS_DRQ_BIT  0x08
+#define DRIVE_LBA_BIT  0x40
+
+#define DEV0 (0)
+#define DEV1 (1)
+
+typedef struct CommandReg {
+    uint8_t data0;
+    union {
+        uint8_t data1;
+        uint8_t error;
+        uint8_t features;
+    };
+    uint8_t sec_count;
+    uint8_t sec_num;
+    uint8_t cyl_low;
+    uint8_t cyl_high;
+    union {
+        uint8_t drive;
+        uint8_t head;
+    };
+    union {
+        uint8_t status;
+        uint8_t command;
+    };
+} CommandReg_t;
+
+typedef enum DevAction {
+    ACT_NONE = 0,
+    ACT_CMD_WRITE,
+    ACT_CMD_COMPLETE,
+    ACT_CMD_ERROR,
+    ACT_STAT_READ,
+    ACT_DATA_READY,
+    ACT_DATA_READ_BYTE,
+    ACT_DATA_READ_SHORT,
+    ACT_DATA_WRITE_BYTE,
+    ACT_DATA_WRITE_SHORT,
+    ACT_DMA_READY,
+    ACT_DMA_DONE
+} DevAction_t;
+
+typedef enum DevState {
+    // Device idle
+    Device_Idle_S = 0,
+    Device_Idle_SI,
+    Device_Idle_NS,
+
+    // Non-data commands
+    Command_Execution,
+
+    // PIO data-in (data to host)
+    Prepare_Data_In,
+    Data_Ready_INTRQ_In,
+    Transfer_Data_In,
+
+    // PIO data-out (data from host)
+    Prepare_Data_Out,
+    Data_Ready_INTRQ_Out,
+    Transfer_Data_Out,
+
+    // DMA protocol
+    Prepare_Data_Dma,
+    Transfer_Data_Dma
+} DevState_t;
+
+typedef enum DmaState {
+    Dma_Idle = 0,
+    Dma_Start,
+    Dma_Transfer
+} DmaState_t;
+
+class PhysicalMemory;
 class IdeController;
 
 /**
- * SCSI Disk device model
+ * IDE Disk device model
  */
 class IdeDisk : public SimObject
 {
   protected:
     /** The IDE controller for this disk. */
     IdeController *ctrl;
+    /** The DMA interface to use for transfers */
+    DMAInterface<Bus> *dmaInterface;
     /** The image that contains the data of this disk. */
     DiskImage *image;
+    /** Pointer to physical memory for DMA transfers */
+    PhysicalMemory *physmem;
 
   protected:
     /** The disk delay in milliseconds. */
     int diskDelay;
 
+  private:
+    /** Drive identification structure for this disk */
+    struct hd_driveid driveID;
+    /** Data buffer for transfers */
+    uint8_t *dataBuffer;
+    /** Number of bytes left in command data transfer */
+    uint32_t cmdBytesLeft;
+    /** Number of bytes left in DRQ block */
+    uint32_t drqBytesLeft;
+    /** Current sector in access */
+    uint32_t curSector;
+    /** Command block registers */
+    CommandReg_t cmdReg;
+    /** Shadow of the current command code */
+    uint8_t curCommand;
+    /** Interrupt enable bit */
+    bool nIENBit;
+    /** Device state */
+    DevState_t devState;
+    /** Dma state */
+    DmaState_t dmaState;
+    /** Dma transaction is a read */
+    bool dmaRead;
+    /** PRD table base address */
+    uint32_t curPrdAddr;
+    /** PRD entry */
+    PrdTableEntry curPrd;
+    /** Device ID (master=0/slave=1) */
+    int devID;
+    /** Interrupt pending */
+    bool intrPending;
+
   public:
     /**
      * Create and initialize this Disk.
      * @param name The name of this disk.
      * @param img The disk image of this disk.
+     * @param phys Pointer to physical memory
+     * @param id The disk ID (master=0/slave=1)
      * @param disk_delay The disk delay in milliseconds
      */
-    IdeDisk(const std::string &name, DiskImage *img, int disk_delay);
+    IdeDisk(const std::string &name, DiskImage *img, PhysicalMemory *phys,
+            int id, int disk_delay);
 
     /**
      * Delete the data buffer.
@@ -71,15 +240,78 @@ class IdeDisk : public SimObject
      * Set the controller for this device
      * @param c The IDE controller
      */
-    void setController(IdeController *c) {
+    void setController(IdeController *c, DMAInterface<Bus> *dmaIntr) {
         if (ctrl) panic("Cannot change the controller once set!\n");
         ctrl = c;
+        dmaInterface = dmaIntr;
     }
 
-    void startIO(uint8_t *cmdBlk, uint8_t *prdPtr) {};
+    // Device register read/write
+    void read(const Addr &offset, bool byte, bool cmdBlk, uint8_t *data);
+    void write(const Addr &offset, bool byte, bool cmdBlk, const uint8_t *data);
+
+    // Start/abort functions
+    void startDma(const uint32_t &prdTableBase);
+    void abortDma();
+
+  private:
+    void startCommand();
+
+    // Interrupt management
+    void intrPost();
+    void intrClear();
+
+    // DMA stuff
+    void doDmaTransfer();
+    friend class EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer>;
+    EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer> dmaTransferEvent;
+
+    void doDmaRead();
+    friend class EventWrapper<IdeDisk, &IdeDisk::doDmaRead>;
+    EventWrapper<IdeDisk, &IdeDisk::doDmaRead> dmaReadWaitEvent;
+
+    void doDmaWrite();
+    friend class EventWrapper<IdeDisk, &IdeDisk::doDmaWrite>;
+    EventWrapper<IdeDisk, &IdeDisk::doDmaWrite> dmaWriteWaitEvent;
 
-    void dmaStart() {};
-    void dmaStop() {};
+    void dmaPrdReadDone();
+    friend class EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone>;
+    EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone> dmaPrdReadEvent;
+
+    void dmaReadDone();
+    friend class EventWrapper<IdeDisk, &IdeDisk::dmaReadDone>;
+    EventWrapper<IdeDisk, &IdeDisk::dmaReadDone> dmaReadEvent;
+
+    void dmaWriteDone();
+    friend class EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone>;
+    EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone> dmaWriteEvent;
+
+    // Disk image read/write
+    void readDisk(uint32_t sector, uint8_t *data);
+    void writeDisk(uint32_t sector, uint8_t *data);
+
+    // State machine management
+    void updateState(DevAction_t action);
+
+    // Utility functions
+    bool isBSYSet() { return (cmdReg.status & STATUS_BSY_BIT); }
+    bool isIENSet() { return nIENBit; }
+    bool isDEVSelect() { return ((cmdReg.drive & SELECT_DEV_BIT) == devID); }
+
+    void setComplete()
+    {
+        // clear out the status byte
+        cmdReg.status = 0;
+
+        // set the DRDY bit
+        cmdReg.status |= STATUS_DRDY_BIT;
+    }
+
+    uint32_t getLBABase()
+    {
+        return  (Addr)(((cmdReg.head & 0xf) << 24) | (cmdReg.cyl_high << 16) |
+                       (cmdReg.cyl_low << 8) | (cmdReg.sec_num));
+    }
 
     /**
      * Serialize this object to the given output stream.