Implement a very very simple bus

requestTime -> time
responseTime -> packet.time

Make CPU and memory able to connect to the bus

dev/io_device.cc:
    update for request and packet both having a time
    hand platform off to port for eventual selection of request modes
dev/io_device.hh:
    update for request and packet both havig a time
    hand platform off to port for eventual selection of request modes
mem/bus.hh:
    Add a device map struct that maps a range to a portId
    - Which needs work it theory it should be an interval tree
    - but it is a list and works fine right now

    Add a function called findPort which returns port for an addr range

    Add a deviceBlockSize function that really shouldn't exist, but it
    was easier than fixing the translating port
mem/packet.hh:
    add a time to each packet
mem/physical.cc:
mem/physical.hh:
python/m5/objects/PhysicalMemory.py:
    Make physical memory take a MemObject parameter of what to connect to
mem/request.hh:
    remove requestTime/responseTime for just time in request which
    is requset time and the time in the packet which is responsetime
python/m5/objects/BaseCPU.py:
    Instead of memory cpu connects to any memory object
python/m5/objects/Bus.py:
    Fix for new bus object

--HG--
extra : convert_revision : 72605e8a3fcdd9e80a41f439909ee7feb3f1fe1d

1 files changed, 6 insertions, 6 deletions

diff --git a/dev/io_device.cc b/dev/io_device.cc
index 268484e57..5f5f9a09d 100644
--- a/dev/io_device.cc
+++ b/dev/io_device.cc
@@ -30,8 +30,8 @@
 #include "sim/builder.hh"
 
 
-PioPort::PioPort(PioDevice *dev)
-        : device(dev)
+PioPort::PioPort(PioDevice *dev, Platform *p)
+        : device(dev), platform(p)
 { }
 
 
@@ -75,7 +75,7 @@ PioPort::SendEvent::process()
 PioDevice::PioDevice(const std::string &name, Platform *p)
     : SimObject(name), platform(p)
 {
-    pioPort = new PioPort(this);
+    pioPort = new PioPort(this, p);
 }
 
 
@@ -83,7 +83,7 @@ bool
 PioPort::recvTiming(Packet &pkt)
 {
     device->recvAtomic(pkt);
-    sendTiming(pkt, pkt.req->responseTime-pkt.req->requestTime);
+    sendTiming(pkt, pkt.time-pkt.req->time);
     return Success;
 }
 
@@ -148,7 +148,7 @@ DmaPort::dmaAction(Command cmd, DmaPort port, Addr addr, int size,
     basePkt.result = Unknown;
     basePkt.req = NULL;
     baseReq.nicReq = true;
-    baseReq.requestTime = curTick;
+    baseReq.time = curTick;
 
     completionEvent = event;
 
@@ -183,7 +183,7 @@ DmaPort::sendDma(Packet &pkt)
            transmitList.push_back(&packet);
    } else if (state == Atomic) {*/
        sendAtomic(pkt);
-       completionEvent->schedule(pkt.req->responseTime - pkt.req->requestTime);
+       completionEvent->schedule(pkt.time - pkt.req->time);
        completionEvent = NULL;
 /*   } else if (state == Functional) {
        sendFunctional(pkt);