Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working

after merge from head. Checkpointing may need some work now. Endian-happiness still not complete.

SConscript:
    add all devices back into make file
base/inet.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pktfifo.cc:
dev/pktfifo.hh:
    rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system
configs/test/fs.py:
    add nics to fs.py
cpu/cpu_exec_context.cc:
    remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the
    static virtual ports in the exec context
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
    use new methods for accessing packet data
dev/ide_disk.cc:
    add some more dprintfs
dev/io_device.cc:
    delete packets when we are done with them. Update for new packet methods to access data
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
dev/uart8250.hh:
mem/physical.cc:
mem/port.cc:
    dUpdate for new packet methods to access data
dev/ns_gige.cc:
    Update for new memory system
dev/ns_gige.hh:
python/m5/objects/Ethernet.py:
    update for new memory system
dev/sinic.cc:
dev/sinic.hh:
    Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions
mem/packet.hh:
    Add methods to access data instead of accessing it directly.

--HG--
extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e

1 files changed, 16 insertions, 9 deletions

diff --git a/dev/io_device.cc b/dev/io_device.cc
index 4a84b6817..42b3c382f 100644
--- a/dev/io_device.cc
+++ b/dev/io_device.cc
@@ -172,7 +172,8 @@ DmaPort::dmaAction(Command cmd, Addr addr, int size, Event *event,
             pkt->req->setPaddr(pkt->addr);
             pkt->req->setSize(pkt->size);
             // Increment the data pointer on a write
-            pkt->data = data ? data + prevSize : NULL ;
+            if (data)
+                pkt->dataStatic(data + prevSize) ;
             prevSize += pkt->size;
             // Set the last bit of the dma as the final packet for this dma
             // and set it's completion event.
@@ -183,13 +184,16 @@ DmaPort::dmaAction(Command cmd, Addr addr, int size, Event *event,
             }
             assert(pendingCount >= 0);
             pendingCount++;
-            sendDma(*pkt);
+            sendDma(pkt);
     }
+    // since this isn't getting used and we want a check to make sure that all
+    // packets had data in them at some point.
+    basePkt.dataStatic((uint8_t*)NULL);
 }
 
 
 void
-DmaPort::sendDma(Packet &pkt)
+DmaPort::sendDma(Packet *pkt)
 {
    // some kind of selction between access methods
    // more work is going to have to be done to make
@@ -200,13 +204,16 @@ DmaPort::sendDma(Packet &pkt)
        if (sendTiming(pkt) == Failure)
            transmitList.push_back(&packet);
    } else if (state == Atomic) {*/
-       sendAtomic(pkt);
-       if (pkt.senderState) {
-           DmaReqState *state = (DmaReqState*)pkt.senderState;
-           state->completionEvent->schedule(curTick + (pkt.time - pkt.req->getTime()) +1);
+       sendAtomic(*pkt);
+       if (pkt->senderState) {
+           DmaReqState *state = (DmaReqState*)pkt->senderState;
+           state->completionEvent->schedule(curTick + (pkt->time - pkt->req->getTime()) +1);
        }
-        pendingCount--;
-        assert(pendingCount >= 0);
+       pendingCount--;
+       assert(pendingCount >= 0);
+       delete pkt->req;
+       delete pkt;
+
 /*   } else if (state == Functional) {
        sendFunctional(pkt);
        // Is this correct???