diff options
| author | Nathan Binkert <binkertn@umich.edu> | 2004-07-12 22:58:22 -0400 |
|---|---|---|
| committer | Nathan Binkert <binkertn@umich.edu> | 2004-07-12 22:58:22 -0400 |
| commit | 13f8dc981fc898e6e200689d305b39f0718f8c83 (patch) | |
| tree | e75ced9115aef60e6c173e08633e19ba92b62569 /dev/ns_gige.cc | |
| parent | c2e5caf3606b85b6f45cde53b8021692ef01710e (diff) | |
| download | gem5-13f8dc981fc898e6e200689d305b39f0718f8c83.tar.xz | |
make the cache access latency a parameter that is based on bus
ticks for the most commonly accessed devices.
dev/baddev.cc:
Get rid of the constant cache access latency.
For unimportant devices, don't add any latency.
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart.cc:
dev/uart.hh:
make the cache access latency a parameter that is based on bus
ticks.
dev/io_device.cc:
dev/io_device.hh:
add an io latency variable
dev/ns_gige.hh:
this moved to io_device.hh
--HG--
extra : convert_revision : 4883130feeaef48abee492eddf0b8eb40eb94789
Diffstat (limited to 'dev/ns_gige.cc')
| -rw-r--r-- | dev/ns_gige.cc | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index 74ace9d99..ff0c90f15 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -120,7 +120,7 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay, acceptMulticast(false), acceptUnicast(false), acceptPerfect(false), acceptArp(false), physmem(pmem), intctrl(i), intrTick(0), cpuPendingIntr(false), - intrEvent(0), interface(0), pioLatency(pio_latency) + intrEvent(0), interface(0) { tsunami->ethernet = this; @@ -128,6 +128,8 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay, pioInterface = newPioInterface(name, hier, header_bus, this, &NSGigE::cacheAccess); + pioLatency = pio_latency * header_bus->clockRatio; + if (payload_bus) dmaInterface = new DMAInterface<Bus>(name + ".dma", header_bus, payload_bus, 1); @@ -138,9 +140,10 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay, pioInterface = newPioInterface(name, hier, payload_bus, this, &NSGigE::cacheAccess); + pioLatency = pio_latency * payload_bus->clockRatio; + dmaInterface = new DMAInterface<Bus>(name + ".dma", payload_bus, payload_bus, 1); - } @@ -2659,7 +2662,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE) INIT_PARAM_DFLT(header_bus, "The IO Bus to attach to for headers", NULL), INIT_PARAM_DFLT(payload_bus, "The IO Bus to attach to for payload", NULL), INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams), - INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000), + INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1), INIT_PARAM_DFLT(dma_desc_free, "DMA of Descriptors is free", false), INIT_PARAM_DFLT(dma_data_free, "DMA of Data is free", false), INIT_PARAM_DFLT(dma_read_delay, "fixed delay for dma reads", 0), |