Fixes for detailed boot, made cttz and ctlz instructions more compact,

and started cleaning up config files.

arch/alpha/isa_desc:
    Made implementation of cttz and ctlz more compact
base/remote_gdb.cc:
    Added comment about PALcode debugger accesses
dev/baddev.cc:
dev/baddev.hh:
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/tsunami_uart.cc:
dev/tsunami_uart.hh:
    Cleaned up includes and changed device from FunctionalMemory to
    PioDevice for detailed boot
dev/ns_gige.cc:
    The ethernet dev uses two BARs, and the first bars size was being set
    incorrectly.
dev/tsunamireg.h:
    I don't know why we were using the superpage as the PCI memory addr.
    Changed and works correctly with detailed boot.

--HG--
extra : convert_revision : b535e76612cb90b544305dc1aa8c5e0e774564bd

1 files changed, 15 insertions, 5 deletions

diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index 812c10df4..fa65b68ab 100644
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -131,8 +131,8 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
         pioInterface = newPioInterface(name, hier, payload_bus, this,
                                        &NSGigE::cacheAccess);
 
-        dmaInterface = new DMAInterface<Bus>(name + ".dma",
-                                             payload_bus, payload_bus, 1);
+        dmaInterface = new DMAInterface<Bus>(name + ".dma", payload_bus,
+                                         payload_bus, 1);
 
     }
 
@@ -244,12 +244,22 @@ NSGigE::WriteConfig(int offset, int size, uint32_t data)
     switch (offset) {
       case PCI0_BASE_ADDR0:
         if (BARAddrs[0] != 0) {
-            addr = BARAddrs[0];
 
             if (pioInterface)
-                pioInterface->addAddrRange(addr, addr + size - 1);
+                pioInterface->addAddrRange(BARAddrs[0], BARAddrs[0] + BARSize[0] - 1);
+
+            BARAddrs[0] &= PA_UNCACHED_MASK;
+
+        }
+        break;
+      case PCI0_BASE_ADDR1:
+        if (BARAddrs[1] != 0) {
+
+            if (pioInterface)
+                pioInterface->addAddrRange(BARAddrs[1], BARAddrs[1] + BARSize[1] - 1);
+
+            BARAddrs[1] &= PA_UNCACHED_MASK;
 
-            addr &= PA_UNCACHED_MASK;
         }
         break;
     }