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| author | Ali Saidi <saidi@eecs.umich.edu> | 2004-10-25 18:14:13 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2004-10-25 18:14:13 -0400 |
| commit | 3402411661caff075890c20a6c59fa471d5e68ac (patch) | |
| tree | 1fdff9005fd8e020217a21bdfac672ff0885b99f /dev/ns_gige.cc | |
| parent | eaf66f46588cdfd8a91b93821406e1d797c6d1fb (diff) | |
| download | gem5-3402411661caff075890c20a6c59fa471d5e68ac.tar.xz | |
changes to make interrupts part of the platform rather than tsunami
specific
--HG--
extra : convert_revision : f51788dd41c23f13b253268bb2b286a5225ef087
Diffstat (limited to 'dev/ns_gige.cc')
| -rw-r--r-- | dev/ns_gige.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc index 9238a7c7e..7260ecde4 100644 --- a/dev/ns_gige.cc +++ b/dev/ns_gige.cc @@ -1038,7 +1038,7 @@ NSGigE::cpuInterrupt() cpuPendingIntr = true; DPRINTF(EthernetIntr, "posting cchip interrupt\n"); - tsunami->cchip->postDRIR(configData->config.hdr.pci0.interruptLine); + tsunami->postPciInt(configData->config.hdr.pci0.interruptLine); } } @@ -1058,7 +1058,7 @@ NSGigE::cpuIntrClear() cpuPendingIntr = false; DPRINTF(EthernetIntr, "clearing cchip interrupt\n"); - tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine); + tsunami->clearPciInt(configData->config.hdr.pci0.interruptLine); } bool |