Merge zed.eecs.umich.edu:/.automount/fox/y/mserrano/m5_dir/m5

into  zed.eecs.umich.edu:/z/benash/bk/m5

dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ide_disk.cc:
dev/ide_disk.hh:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/pcidev.cc:
dev/rtcreg.h:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/uart8250.cc:
dev/uart8250.hh:
python/m5/objects/Tsunami.py:
    Merge code.

--HG--
extra : convert_revision : e97d5dbcc051d2061622201265430d359f995d48

1 files changed, 6 insertions, 6 deletions

diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index ae129c249..304263695 100644
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -491,10 +491,10 @@ NSGigE::regStats()
  * This is to read the PCI general configuration registers
  */
 void
-NSGigE::ReadConfig(int offset, int size, uint8_t *data)
+NSGigE::readConfig(int offset, int size, uint8_t *data)
 {
     if (offset < PCI_DEVICE_SPECIFIC)
-        PciDev::ReadConfig(offset, size, data);
+        PciDev::readConfig(offset, size, data);
     else
         panic("Device specific PCI config space not implemented!\n");
 }
@@ -503,10 +503,10 @@ NSGigE::ReadConfig(int offset, int size, uint8_t *data)
  * This is to write to the PCI general configuration registers
  */
 void
-NSGigE::WriteConfig(int offset, int size, uint32_t data)
+NSGigE::writeConfig(int offset, int size, const uint8_t* data)
 {
     if (offset < PCI_DEVICE_SPECIFIC)
-        PciDev::WriteConfig(offset, size, data);
+        PciDev::writeConfig(offset, size, data);
     else
         panic("Device specific PCI config space not implemented!\n");
 
@@ -577,7 +577,7 @@ NSGigE::read(MemReqPtr &req, uint8_t *data)
     if (daddr > LAST && daddr <=  RESERVED) {
         panic("Accessing reserved register");
     } else if (daddr > RESERVED && daddr <= 0x3FC) {
-        ReadConfig(daddr & 0xff, req->size, data);
+        readConfig(daddr & 0xff, req->size, data);
         return No_Fault;
     } else if (daddr >= MIB_START && daddr <= MIB_END) {
         // don't implement all the MIB's.  hopefully the kernel
@@ -797,7 +797,7 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
     if (daddr > LAST && daddr <=  RESERVED) {
         panic("Accessing reserved register");
     } else if (daddr > RESERVED && daddr <= 0x3FC) {
-        WriteConfig(daddr & 0xff, req->size, *(uint32_t *)data);
+        writeConfig(daddr & 0xff, req->size, data);
         return No_Fault;
     } else if (daddr > 0x3FC)
         panic("Something is messed up!\n");