Standardize clock parameter names to 'clock'.

Fix description for Bus clock_ratio (no longer a ratio).
Add Clock param type (generic Frequency or Latency).

cpu/base_cpu.cc:
cpu/base_cpu.hh:
cpu/beta_cpu/alpha_full_cpu_builder.cc:
cpu/simple_cpu/simple_cpu.cc:
dev/ide_ctrl.cc:
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/pciconfigall.cc:
dev/sinic.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
python/m5/objects/BaseCPU.py:
python/m5/objects/BaseCache.py:
python/m5/objects/BaseSystem.py:
python/m5/objects/Bus.py:
python/m5/objects/Ethernet.py:
python/m5/objects/Root.py:
sim/universe.cc:
    Standardize clock parameter names to 'clock'.
    Fix description for Bus clock_ratio (no longer a ratio).
python/m5/config.py:
    Minor tweaks on Frequency/Latency:
    - added new Clock param type to avoid ambiguities
    - factored out init code into getLatency()
    - made RootFrequency *not* a subclass of Frequency so it
    can't be directly assigned to a Frequency paremeter

--HG--
extra : convert_revision : fc4bb8562df171b454bbf696314cda57e1ec8506

1 files changed, 3 insertions, 3 deletions

diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index cbb7185e7..302aa5a89 100644
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -176,8 +176,8 @@ class NSGigE : public PciDev
     ns_desc rxDescCache;
 
     /* state machine cycle time */
-    Tick cycleTime;
-    inline Tick cycles(int numCycles) const { return numCycles * cycleTime; }
+    Tick clock;
+    inline Tick cycles(int numCycles) const { return numCycles * clock; }
 
     /* tx State Machine */
     TxState txState;
@@ -328,7 +328,7 @@ class NSGigE : public PciDev
         HierParams *hier;
         Bus *header_bus;
         Bus *payload_bus;
-        Tick cycle_time;
+        Tick clock;
         Tick intr_delay;
         Tick tx_delay;
         Tick rx_delay;