make the cache access latency a parameter that is based on bus

ticks for the most commonly accessed devices.

dev/baddev.cc:
    Get rid of the constant cache access latency.
    For unimportant devices, don't add any latency.
dev/ide_ctrl.cc:
dev/ide_ctrl.hh:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/pciconfigall.hh:
dev/tsunami_cchip.cc:
dev/tsunami_cchip.hh:
dev/tsunami_io.cc:
dev/tsunami_io.hh:
dev/tsunami_pchip.cc:
dev/tsunami_pchip.hh:
dev/uart.cc:
dev/uart.hh:
    make the cache access latency a parameter that is based on bus
    ticks.
dev/io_device.cc:
dev/io_device.hh:
    add an io latency variable
dev/ns_gige.hh:
    this moved to io_device.hh

--HG--
extra : convert_revision : 4883130feeaef48abee492eddf0b8eb40eb94789

1 files changed, 0 insertions, 3 deletions

diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index 55cc92a2c..79ae00e64 100644
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -383,9 +383,6 @@ class NSGigE : public PciDev
     Stats::Formula txPacketRate;
     Stats::Formula rxPacketRate;
 
-  private:
-    Tick pioLatency;
-
   public:
     Tick cacheAccess(MemReqPtr &req);
 };