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authorSteve Reinhardt <stever@eecs.umich.edu>2004-10-24 23:06:35 -0400
committerSteve Reinhardt <stever@eecs.umich.edu>2004-10-24 23:06:35 -0400
commit400daa7e41057ec358691afeffe35ffa430d11b0 (patch)
tree06eaf8242206a12eb7a14281c7d112984c02ac89 /dev/ns_gige.hh
parent7c58c38e668ff4057820f8c6ee8cd8169b934051 (diff)
parent6ac0d27b7dc130397b6ba9b11e593706c2f669fe (diff)
downloadgem5-400daa7e41057ec358691afeffe35ffa430d11b0.tar.xz
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/stever/bk/m5 --HG-- extra : convert_revision : aac76a4b82b3455620618bba6238507248cc68cc
Diffstat (limited to 'dev/ns_gige.hh')
-rw-r--r--dev/ns_gige.hh18
1 files changed, 8 insertions, 10 deletions
diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index b7838cf6f..60dcf3fc2 100644
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -31,9 +31,10 @@
* DP83820 ethernet controller
*/
-#ifndef __NS_GIGE_HH__
-#define __NS_GIGE_HH__
+#ifndef __DEV_NS_GIGE_HH__
+#define __DEV_NS_GIGE_HH__
+#include "base/inet.hh"
#include "base/statistics.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
@@ -44,9 +45,6 @@
#include "mem/bus/bus.hh"
#include "sim/eventq.hh"
-/** length of ethernet address in bytes */
-#define EADDR_LEN 6
-
/**
* Ethernet device registers
*/
@@ -90,7 +88,7 @@ struct dp_rom {
* for perfect match memory.
* the linux driver doesn't use any other ROM
*/
- uint8_t perfectMatch[EADDR_LEN];
+ uint8_t perfectMatch[ETH_ADDR_LEN];
};
class IntrControl;
@@ -302,7 +300,7 @@ class NSGigE : public PciDev
* receive address filter
*/
bool rxFilterEnable;
- bool rxFilter(PacketPtr packet);
+ bool rxFilter(PacketPtr &packet);
bool acceptBroadcast;
bool acceptMulticast;
bool acceptUnicast;
@@ -339,7 +337,7 @@ class NSGigE : public PciDev
bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
- uint32_t func, bool rx_filter, const int eaddr[6],
+ uint32_t func, bool rx_filter, Net::EthAddr eaddr,
uint32_t tx_fifo_size, uint32_t rx_fifo_size);
~NSGigE();
@@ -352,7 +350,7 @@ class NSGigE : public PciDev
bool cpuIntrPending() const;
void cpuIntrAck() { cpuIntrClear(); }
- bool recvPacket(PacketPtr packet);
+ bool recvPacket(PacketPtr &packet);
void transferDone();
void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
@@ -403,4 +401,4 @@ class NSGigEInt : public EtherInt
virtual void sendDone() { dev->transferDone(); }
};
-#endif // __NS_GIGE_HH__
+#endif // __DEV_NS_GIGE_HH__