Get rid of the code that delays PIO write accesses

until the cache access occurs.  The fundamental problem
is that a subsequent read that occurs functionally will
get a functionally incorrect result that can break
driver code.

dev/ns_gige.cc:
dev/ns_gige.hh:
dev/sinic.cc:
dev/sinic.hh:
    get rid of pio_delay write and the associated code to move
    the write to the cache access function
dev/sinicreg.hh:
    no more write delays
python/m5/objects/Ethernet.py:
    get rid of pio_delay write

--HG--
extra : convert_revision : 1dcb51b8f4514e717bc334a782dfdf06d29ae69d

1 files changed, 0 insertions, 10 deletions

diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index 181837c8d..a14fde146 100644
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -236,15 +236,6 @@ class NSGigE : public PciDev
     uint32_t rxDescCnt;
     DmaState rxDmaState;
 
-    struct RegWriteData {
-        Addr daddr;
-        uint32_t value;
-        RegWriteData(Addr da, uint32_t val) : daddr(da), value(val) {}
-    };
-
-    std::vector<std::list<RegWriteData> > writeQueue;
-    bool pioDelayWrite;
-
     bool extstsEnable;
 
     /** EEPROM State Machine */
@@ -382,7 +373,6 @@ class NSGigE : public PciDev
         Tick tx_delay;
         Tick rx_delay;
         Tick pio_latency;
-        bool pio_delay_write;
         bool dma_desc_free;
         bool dma_data_free;
         Tick dma_read_delay;