add support for delaying pio writes until the cache access occurs

dev/ns_gige.cc:
    add support for delaying pio writes until the cache access occurs
    the only write we delay are for CR_TXE and CR_RXE
dev/sinic.cc:
dev/sinic.hh:
    the txPioRequest and rxPioRequest things were more or less bogus
    add support for delaying pio writes until the cache access occurs
dev/sinicreg.hh:
    Add delay_read and delay_write to the register information struct
    for now, we won't delay any reads, and we'll delay the writes that
    initiate DMAs
python/m5/objects/Ethernet.py:
    add a parameter to delay pio writes until the timing access
    actually occurs.

--HG--
extra : convert_revision : 79b18ea2812c2935d7d5ea6eff1f55265114d05d

1 files changed, 10 insertions, 0 deletions

diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index 36fd6050a..7db833028 100644
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -239,6 +239,15 @@ class NSGigE : public PciDev
     uint32_t rxDescCnt;
     DmaState rxDmaState;
 
+    struct RegWriteData {
+        Addr daddr;
+        uint32_t value;
+        RegWriteData(Addr da, uint32_t val) : daddr(da), value(val) {}
+    };
+
+    std::vector<std::list<RegWriteData> > writeQueue;
+    bool pioDelayWrite;
+
     bool extstsEnable;
 
     /** EEPROM State Machine */
@@ -376,6 +385,7 @@ class NSGigE : public PciDev
         Tick tx_delay;
         Tick rx_delay;
         Tick pio_latency;
+        bool pio_delay_write;
         bool dma_desc_free;
         bool dma_data_free;
         Tick dma_read_delay;