Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working

after merge from head. Checkpointing may need some work now. Endian-happiness still not complete.

SConscript:
    add all devices back into make file
base/inet.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pktfifo.cc:
dev/pktfifo.hh:
    rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system
configs/test/fs.py:
    add nics to fs.py
cpu/cpu_exec_context.cc:
    remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the
    static virtual ports in the exec context
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
    use new methods for accessing packet data
dev/ide_disk.cc:
    add some more dprintfs
dev/io_device.cc:
    delete packets when we are done with them. Update for new packet methods to access data
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
dev/uart8250.hh:
mem/physical.cc:
mem/port.cc:
    dUpdate for new packet methods to access data
dev/ns_gige.cc:
    Update for new memory system
dev/ns_gige.hh:
python/m5/objects/Ethernet.py:
    update for new memory system
dev/sinic.cc:
dev/sinic.hh:
    Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions
mem/packet.hh:
    Add methods to access data instead of accessing it directly.

--HG--
extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e

1 files changed, 9 insertions, 33 deletions

diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index 59c55056e..7bb422287 100644
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -42,7 +42,6 @@
 #include "dev/ns_gige_reg.h"
 #include "dev/pcidev.hh"
 #include "dev/pktfifo.hh"
-#include "mem/bus/bus.hh"
 #include "sim/eventq.hh"
 
 // Hash filtering constants
@@ -111,10 +110,7 @@ struct dp_rom {
 };
 
 class NSGigEInt;
-class PhysicalMemory;
-class BaseInterface;
-class HierParams;
-class Bus;
+class Packet;
 class PciConfigAll;
 
 /**
@@ -165,10 +161,6 @@ class NSGigE : public PciDev
         eepromRead
     };
 
-  private:
-    Addr addr;
-    static const Addr size = sizeof(dp_regs);
-
   protected:
     /** device register file */
     dp_regs regs;
@@ -187,8 +179,8 @@ class NSGigE : public PciDev
     PacketFifo rxFifo;
 
     /** various helper vars */
-    PacketPtr txPacket;
-    PacketPtr rxPacket;
+    EthPacketPtr txPacket;
+    EthPacketPtr rxPacket;
     uint8_t *txPacketBufPtr;
     uint8_t *rxPacketBufPtr;
     uint32_t txXferLen;
@@ -258,16 +250,12 @@ class NSGigE : public PciDev
     int   rxDmaLen;
     bool  doRxDmaRead();
     bool  doRxDmaWrite();
-    void  rxDmaReadCopy();
-    void  rxDmaWriteCopy();
 
     void *txDmaData;
     Addr  txDmaAddr;
     int   txDmaLen;
     bool  doTxDmaRead();
     bool  doTxDmaWrite();
-    void  txDmaReadCopy();
-    void  txDmaWriteCopy();
 
     void rxDmaReadDone();
     friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>;
@@ -331,7 +319,7 @@ class NSGigE : public PciDev
      * receive address filter
      */
     bool rxFilterEnable;
-    bool rxFilter(const PacketPtr &packet);
+    bool rxFilter(const EthPacketPtr &packet);
     bool acceptBroadcast;
     bool acceptMulticast;
     bool acceptUnicast;
@@ -339,8 +327,6 @@ class NSGigE : public PciDev
     bool acceptArp;
     bool multicastHashEnable;
 
-    PhysicalMemory *physmem;
-
     /**
      * Interrupt management
      */
@@ -363,16 +349,10 @@ class NSGigE : public PciDev
   public:
     struct Params : public PciDev::Params
     {
-        PhysicalMemory *pmem;
-        HierParams *hier;
-        Bus *pio_bus;
-        Bus *header_bus;
-        Bus *payload_bus;
         Tick clock;
         Tick intr_delay;
         Tick tx_delay;
         Tick rx_delay;
-        Tick pio_latency;
         bool dma_desc_free;
         bool dma_data_free;
         Tick dma_read_delay;
@@ -393,16 +373,15 @@ class NSGigE : public PciDev
     ~NSGigE();
     const Params *params() const { return (const Params *)_params; }
 
-    virtual void writeConfig(int offset, int size, const uint8_t *data);
-    virtual void readConfig(int offset, int size, uint8_t *data);
+    virtual void writeConfig(int offset, const uint16_t data);
 
-    virtual Fault read(MemReqPtr &req, uint8_t *data);
-    virtual Fault write(MemReqPtr &req, const uint8_t *data);
+    virtual Tick read(Packet &pkt);
+    virtual Tick write(Packet &pkt);
 
     bool cpuIntrPending() const;
     void cpuIntrAck() { cpuIntrClear(); }
 
-    bool recvPacket(PacketPtr packet);
+    bool recvPacket(EthPacketPtr packet);
     void transferDone();
 
     void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
@@ -463,9 +442,6 @@ class NSGigE : public PciDev
     Stats::Formula coalescedTotal;
     Stats::Scalar<> postedInterrupts;
     Stats::Scalar<> droppedPackets;
-
-  public:
-    Tick cacheAccess(MemReqPtr &req);
 };
 
 /*
@@ -480,7 +456,7 @@ class NSGigEInt : public EtherInt
     NSGigEInt(const std::string &name, NSGigE *d)
         : EtherInt(name), dev(d) { dev->setInterface(this); }
 
-    virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); }
+    virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); }
     virtual void sendDone() { dev->transferDone(); }
 };