make tx/rx fifo size a param, also fix the empty dma problem by adjusting the state machine.

dev/ns_gige.cc:
    make tx/rx fifo sizes a param. the default is 128K for each.  also, make the state machine not move onto txFragRead if there is no room in the txfifo for data.
dev/ns_gige.hh:
    make tx/rx fifo size a param

--HG--
extra : convert_revision : ed91eb31c2b21d4cdc6de87d8641df6197be5209

1 files changed, 13 insertions, 9 deletions

diff --git a/dev/ns_gige.hh b/dev/ns_gige.hh
index a8d8d1f18..55cc92a2c 100644
--- a/dev/ns_gige.hh
+++ b/dev/ns_gige.hh
@@ -46,8 +46,9 @@
 #include "mem/bus/bus.hh"
 
 /** defined by the NS83820 data sheet */
-#define MAX_TX_FIFO_SIZE 8192
-#define MAX_RX_FIFO_SIZE 32768
+//these are now params for the device
+//#define MAX_TX_FIFO_SIZE 8192
+//#define MAX_RX_FIFO_SIZE 32768
 
 /** length of ethernet address in bytes */
 #define EADDR_LEN 6
@@ -168,7 +169,9 @@ class NSGigE : public PciDev
     /*** BASIC STRUCTURES FOR TX/RX ***/
     /* Data FIFOs */
     pktbuf_t txFifo;
+    uint32_t maxTxFifoSize;
     pktbuf_t rxFifo;
+    uint32_t maxRxFifoSize;
 
     /** various helper vars */
     PacketPtr txPacket;
@@ -332,13 +335,14 @@ class NSGigE : public PciDev
 
   public:
     NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
-             PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay,
-             MemoryController *mmu, HierParams *hier, Bus *header_bus,
-             Bus *payload_bus, Tick pio_latency, bool dma_desc_free,
-             bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
-             Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
-             PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
-             uint32_t func, bool rx_filter, const int eaddr[6]);
+           PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay,
+           MemoryController *mmu, HierParams *hier, Bus *header_bus,
+           Bus *payload_bus, Tick pio_latency, bool dma_desc_free,
+           bool dma_data_free, Tick dma_read_delay, Tick dma_write_delay,
+           Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
+           PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
+           uint32_t func, bool rx_filter, const int eaddr[6],
+           uint32_t tx_fifo_size, uint32_t rx_fifo_size);
     ~NSGigE();
 
     virtual void WriteConfig(int offset, int size, uint32_t data);