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authorNathan Binkert <binkertn@umich.edu>2004-07-12 22:58:22 -0400
committerNathan Binkert <binkertn@umich.edu>2004-07-12 22:58:22 -0400
commit13f8dc981fc898e6e200689d305b39f0718f8c83 (patch)
treee75ced9115aef60e6c173e08633e19ba92b62569 /dev/pciconfigall.cc
parentc2e5caf3606b85b6f45cde53b8021692ef01710e (diff)
downloadgem5-13f8dc981fc898e6e200689d305b39f0718f8c83.tar.xz
make the cache access latency a parameter that is based on bus
ticks for the most commonly accessed devices. dev/baddev.cc: Get rid of the constant cache access latency. For unimportant devices, don't add any latency. dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ns_gige.cc: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/uart.cc: dev/uart.hh: make the cache access latency a parameter that is based on bus ticks. dev/io_device.cc: dev/io_device.hh: add an io latency variable dev/ns_gige.hh: this moved to io_device.hh --HG-- extra : convert_revision : 4883130feeaef48abee492eddf0b8eb40eb94789
Diffstat (limited to 'dev/pciconfigall.cc')
-rw-r--r--dev/pciconfigall.cc10
1 files changed, 7 insertions, 3 deletions
diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc
index 8937b8e67..740a9b4ac 100644
--- a/dev/pciconfigall.cc
+++ b/dev/pciconfigall.cc
@@ -47,7 +47,7 @@
using namespace std;
PciConfigAll::PciConfigAll(const string &name, Addr a, MemoryController *mmu,
- HierParams *hier, Bus *bus)
+ HierParams *hier, Bus *bus, Tick pio_latency)
: PioDevice(name), addr(a)
{
mmu->add_child(this, Range<Addr>(addr, addr + size));
@@ -56,6 +56,7 @@ PciConfigAll::PciConfigAll(const string &name, Addr a, MemoryController *mmu,
pioInterface = newPioInterface(name, hier, bus, this,
&PciConfigAll::cacheAccess);
pioInterface->addAddrRange(addr, addr + size - 1);
+ pioLatency = pio_latency * bus->clockRatio;
}
// Make all the pointers to devices null
@@ -175,7 +176,7 @@ PciConfigAll::unserialize(Checkpoint *cp, const std::string &section)
Tick
PciConfigAll::cacheAccess(MemReqPtr &req)
{
- return curTick + 1000;
+ return curTick + pioLatency;
}
#ifndef DOXYGEN_SHOULD_SKIP_THIS
@@ -186,6 +187,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
Param<Addr> addr;
Param<Addr> mask;
SimObjectParam<Bus*> io_bus;
+ Param<Tick> pio_latency;
SimObjectParam<HierParams *> hier;
END_DECLARE_SIM_OBJECT_PARAMS(PciConfigAll)
@@ -196,13 +198,15 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
INIT_PARAM(addr, "Device Address"),
INIT_PARAM(mask, "Address Mask"),
INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
+ INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
END_INIT_SIM_OBJECT_PARAMS(PciConfigAll)
CREATE_SIM_OBJECT(PciConfigAll)
{
- return new PciConfigAll(getInstanceName(), addr, mmu, hier, io_bus);
+ return new PciConfigAll(getInstanceName(), addr, mmu, hier, io_bus,
+ pio_latency);
}
REGISTER_SIM_OBJECT("PciConfigAll", PciConfigAll)