diff options
| author | Benjamin Nash <benash@umich.edu> | 2005-07-28 13:16:45 -0400 |
|---|---|---|
| committer | Benjamin Nash <benash@umich.edu> | 2005-07-28 13:16:45 -0400 |
| commit | a115249eb07f6e3c9666bf408e214fcd38a665fb (patch) | |
| tree | 21ea53a2698dc89fdc7f26fc81d45db6d69fbe4f /dev/pcidev.cc | |
| parent | 648c3beb1d4735e423e77f5189c27c28e5b34493 (diff) | |
| parent | 74fd4f68c5a7df2efba11497ba1ab5ab62b0b1bf (diff) | |
| download | gem5-a115249eb07f6e3c9666bf408e214fcd38a665fb.tar.xz | |
Merge zed.eecs.umich.edu:/.automount/fox/y/mserrano/m5_new/m5
into zed.eecs.umich.edu:/z/benash/bk/m5
SConscript:
dev/ide_disk.hh:
Formatting.
dev/ide_ctrl.cc:
Endianness
dev/ide_disk.cc:
dev/pcidev.cc:
dev/tsunami_io.cc:
dev/uart8250.cc:
Clean up code.
--HG--
extra : convert_revision : cb554f0e3a701371d2106cd7e11a4a22f773acc2
Diffstat (limited to 'dev/pcidev.cc')
| -rw-r--r-- | dev/pcidev.cc | 12 |
1 files changed, 4 insertions, 8 deletions
diff --git a/dev/pcidev.cc b/dev/pcidev.cc index 31c44bffa..c74fb035c 100644 --- a/dev/pcidev.cc +++ b/dev/pcidev.cc @@ -115,10 +115,6 @@ PciDev::WriteConfig(int offset, int size, uint32_t data) uint32_t barnum; - uint8_t byte_value; - uint16_t half_value; - uint32_t word_value; - DPRINTF(PCIDEV, "write device: %#x function: %#x reg: %#x size: %d data: %#x\n", params()->deviceNum, params()->functionNum, offset, size, @@ -128,7 +124,7 @@ PciDev::WriteConfig(int offset, int size, uint32_t data) switch (size) { case sizeof(uint8_t): // 1-byte access - byte_value = data; + uint8_t byte_value = data; switch (offset) { case PCI0_INTERRUPT_LINE: case PCI_CACHE_LINE_SIZE: @@ -148,7 +144,7 @@ PciDev::WriteConfig(int offset, int size, uint32_t data) break; case sizeof(uint16_t): // 2-byte access - half_value = data; + uint16_t half_value = data; switch (offset) { case PCI_COMMAND: case PCI_STATUS: @@ -162,7 +158,7 @@ PciDev::WriteConfig(int offset, int size, uint32_t data) break; case sizeof(uint32_t): // 4-byte access - word_value = data; + uint32_t word_value = data; switch (offset) { case PCI0_BASE_ADDR0: case PCI0_BASE_ADDR1: @@ -194,7 +190,7 @@ PciDev::WriteConfig(int offset, int size, uint32_t data) htoa((word_value & ~0x3) | (htoa(config.data[offset]) & 0x3)); - if (word_value != 0x1) { + if (word_value &= ~0x1) { Addr base_addr = (word_value & ~0x1) + TSUNAMI_PCI0_IO; Addr base_size = BARSize[barnum]; |