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authorBenjamin Nash <benash@umich.edu>2005-06-09 15:01:15 -0400
committerBenjamin Nash <benash@umich.edu>2005-06-09 15:01:15 -0400
commitc4fdfa3844ec0e1ae6f34660024ee33170445b8d (patch)
tree172be4e7ad9e9361efff8b745197883d0035f7fb /dev/pcidev.cc
parent4cc9fbf61d70668a8d80681998a1db2b2e1b4a41 (diff)
downloadgem5-c4fdfa3844ec0e1ae6f34660024ee33170445b8d.tar.xz
Mostly IO modifications, to increase compatibility with FreeBSD.
dev/pcidev.cc: Allow writes to some PCI read-only registers. Fix problem when writing to a zero offset IO location. dev/tsunami_io.cc: Fix calculation of IO addresses. Add registers for keyboard and PCI DMA. dev/tsunamireg.h: Add registers for keyboard and PCI DMA. python/m5/objects/System.py: Allow generic System to be instantiated. --HG-- extra : convert_revision : 1b985ffa2b8e15aa55246f1d14da615c32ecd3f9
Diffstat (limited to 'dev/pcidev.cc')
-rw-r--r--dev/pcidev.cc10
1 files changed, 8 insertions, 2 deletions
diff --git a/dev/pcidev.cc b/dev/pcidev.cc
index f2bce33ca..93200a8c7 100644
--- a/dev/pcidev.cc
+++ b/dev/pcidev.cc
@@ -138,7 +138,13 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
case PCI_LATENCY_TIMER:
*(uint8_t *)&config.data[offset] = htoa(byte_value);
break;
-
+ /* Do nothing for these read-only registers */
+ case PCI0_INTERRUPT_PIN:
+ case PCI0_MINIMUM_GRANT:
+ case PCI0_MAXIMUM_LATENCY:
+ case PCI_CLASS_CODE:
+ case PCI_REVISION_ID:
+ break;
default:
panic("writing to a read only register");
}
@@ -192,7 +198,7 @@ PciDev::WriteConfig(int offset, int size, uint32_t data)
htoa((word_value & ~0x3) |
(htoa(config.data[offset]) & 0x3));
- if (word_value & ~0x1) {
+ if (word_value != 0x1) {
Addr base_addr = (word_value & ~0x1) + TSUNAMI_PCI0_IO;
Addr base_size = BARSize[barnum];