Merge zizzer:/bk/multiarch

into  zazzer.eecs.umich.edu:/z/ksewell/research/m5-sim/m5-multiarch

--HG--
extra : convert_revision : 17b164847aee7e21d15d1a9d99aae43f46906c28

1 files changed, 20 insertions, 20 deletions

diff --git a/dev/pcidev.hh b/dev/pcidev.hh
index efc805b3f..c8d9685c1 100644
--- a/dev/pcidev.hh
+++ b/dev/pcidev.hh
@@ -189,37 +189,37 @@ class PciDev : public DmaDevice
      */
     PciDev(Params *params);
 
-    virtual Fault read(MemReqPtr &req, uint8_t *data);
-    virtual Fault write(MemReqPtr &req, const uint8_t *data);
+    virtual Fault * read(MemReqPtr &req, uint8_t *data);
+    virtual Fault * write(MemReqPtr &req, const uint8_t *data);
 
   public:
     /**
      * Implement the read/write as BAR accesses
      */
-    Fault readBar(MemReqPtr &req, uint8_t *data);
-    Fault writeBar(MemReqPtr &req, const uint8_t *data);
+    Fault * readBar(MemReqPtr &req, uint8_t *data);
+    Fault * writeBar(MemReqPtr &req, const uint8_t *data);
 
   public:
     /**
      * Read from a specific BAR
      */
-    virtual Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
-    virtual Fault readBar1(MemReqPtr &req, Addr daddr, uint8_t *data);
-    virtual Fault readBar2(MemReqPtr &req, Addr daddr, uint8_t *data);
-    virtual Fault readBar3(MemReqPtr &req, Addr daddr, uint8_t *data);
-    virtual Fault readBar4(MemReqPtr &req, Addr daddr, uint8_t *data);
-    virtual Fault readBar5(MemReqPtr &req, Addr daddr, uint8_t *data);
+    virtual Fault * readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
+    virtual Fault * readBar1(MemReqPtr &req, Addr daddr, uint8_t *data);
+    virtual Fault * readBar2(MemReqPtr &req, Addr daddr, uint8_t *data);
+    virtual Fault * readBar3(MemReqPtr &req, Addr daddr, uint8_t *data);
+    virtual Fault * readBar4(MemReqPtr &req, Addr daddr, uint8_t *data);
+    virtual Fault * readBar5(MemReqPtr &req, Addr daddr, uint8_t *data);
 
   public:
     /**
      * Write to a specific BAR
      */
-    virtual Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
-    virtual Fault writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data);
-    virtual Fault writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data);
-    virtual Fault writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data);
-    virtual Fault writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data);
-    virtual Fault writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data);
+    virtual Fault * writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
+    virtual Fault * writeBar1(MemReqPtr &req, Addr daddr, const uint8_t *data);
+    virtual Fault * writeBar2(MemReqPtr &req, Addr daddr, const uint8_t *data);
+    virtual Fault * writeBar3(MemReqPtr &req, Addr daddr, const uint8_t *data);
+    virtual Fault * writeBar4(MemReqPtr &req, Addr daddr, const uint8_t *data);
+    virtual Fault * writeBar5(MemReqPtr &req, Addr daddr, const uint8_t *data);
 
   public:
     /**
@@ -257,7 +257,7 @@ class PciDev : public DmaDevice
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 };
 
-inline Fault
+inline Fault *
 PciDev::readBar(MemReqPtr &req, uint8_t *data)
 {
     if (isBAR(req->paddr, 0))
@@ -272,10 +272,10 @@ PciDev::readBar(MemReqPtr &req, uint8_t *data)
         return readBar4(req, req->paddr - BARAddrs[4], data);
     if (isBAR(req->paddr, 5))
         return readBar5(req, req->paddr - BARAddrs[5], data);
-    return Machine_Check_Fault;
+    return MachineCheckFault;
 }
 
-inline Fault
+inline Fault *
 PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
 {
     if (isBAR(req->paddr, 0))
@@ -290,7 +290,7 @@ PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
         return writeBar4(req, req->paddr - BARAddrs[4], data);
     if (isBAR(req->paddr, 5))
         return writeBar5(req, req->paddr - BARAddrs[5], data);
-    return Machine_Check_Fault;
+    return MachineCheckFault;
 }
 
 #endif // __DEV_PCIDEV_HH__