Changes for getting FreeBSD to run.

SConscript:
    Added more files to compile: dev/pcifake.cc, dev/isa_fake.cc, kern/freebsd/freebsd_system.cc, kern/freebsd/freebsd_events.cc.
arch/alpha/isa_traits.hh:
    Added constant for argument register 2 as it is needed by FreebsdSystem::doCalibrateClocks().
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
    Replaced htoa()s with gtoh() and htog().
cpu/o3/fetch_impl.hh:
cpu/simple/cpu.cc:
    Replaced htoa() with gtoh().
dev/disk_image.cc:
    Replaced htoa()s with letoh()s.
dev/ide_ctrl.cc:
    Got rid of magic numbers.
    Added IdeChannel and IdeRegType type names where necessary.
dev/ide_ctrl.hh:
    Got rid of unnecessary macros.
    Changed RegType_t to IdeRegType.
    Changed bmi_regs to allow accessing registers by name instead of just by array index.
    Added IdeChannel enum type to use in place of bool variables which were used to specify IDE channel.
dev/ide_disk.cc:
    Rewrote IdeDisk::read and IdeDisk::write functions to specify registers by name instead of indexing through an array.
dev/ide_disk.hh:
    Updated command register struct.
dev/ns_gige.cc:
dev/ns_gige.hh:
    Made ReadConfig and WriteConfig begin with a lower-case letter.
    writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pciconfigall.cc:
    writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pcidev.cc:
    Cleaned up readConfig() and writeConfig() functions.
dev/pcidev.hh:
    Added macros to make code that works with the BARs (base adress registers) more readable. writeConfig() now takes a pointer to data.
dev/pcireg.h:
    Changed PCIConfig struct to make accessing elements more straight forward. Removed type 1 (for PCI-to-PCI bridges) PCI configuration space struct since it is not used.
dev/rtcreg.h:
    Added macros for bit fields in RTC status registers A & B.
dev/sinic.cc:
    Function name change: WriteConfig --> writeConfig.
    writeConfig() now takes a pointer to data instead of a copy of data.
    The accessing of elements of PCIConfig structure is updated.
dev/sinic.hh:
    Function name change: WriteConfig --> writeConfig.
    writeConfig() now takes a pointer to data instead of a copy of data.
dev/tsunami_io.cc:
    Added implementation of new RTC and PIT classes.
dev/tsunami_io.hh:
    Added classes for RTC and PIT modules.
dev/tsunamireg.h:
    Added macros for DMA ports used by Tsunami-Tru64.
dev/uart8250.cc:
    Got rid of a magic number.
    Transmit (Tx) interrupts should clear upon a read of the Interrupt ID register.
dev/uart8250.hh:
    Added comments and macros dealing with the UART Interrupt ID register.
kern/linux/linux_system.cc:
    Replaced htoa() with htog().
python/m5/objects/Pci.py:
    PciFake is a python class for Pci Devices that do nothing.
python/m5/objects/Tsunami.py:
    TsunamiFake was renamed as IsaFake.
sim/system.cc:
    Replaced htoa()s with htog()s.
dev/isa_fake.cc:
    New BitKeeper file ``dev/isa_fake.cc''
    TsunamiFake was renamed as IsaFake.
dev/isa_fake.hh:
    New BitKeeper file ``dev/isa_fake.hh''
    TsunmaiFake was renamed as IsaFake.
dev/pitreg.h:
    New BitKeeper file ``dev/pitreg.h''
    Useful macros for working with PIT (Periodic Interval Timer) registers.

--HG--
extra : convert_revision : 33f3a8a1034af4f6c71b32dd743e371c8613e780

1 files changed, 33 insertions, 57 deletions

diff --git a/dev/pcireg.h b/dev/pcireg.h
index 2f71a46ba..9d2737c20 100644
--- a/dev/pcireg.h
+++ b/dev/pcireg.h
@@ -36,68 +36,44 @@
 #include <sys/types.h>
 
 union PCIConfig {
-    uint8_t	data[64];
-
-    struct hdr {
-        uint16_t	vendor;
-        uint16_t	device;
-        uint16_t	command;
-        uint16_t	status;
-        uint8_t		revision;
-        uint8_t		progIF;
-        uint8_t		subClassCode;
-        uint8_t		classCode;
-        uint8_t		cacheLineSize;
-        uint8_t		latencyTimer;
-        uint8_t		headerType;
-        uint8_t		bist;
+    uint8_t data[64];
 
+    struct {
+        uint16_t vendor;
+        uint16_t device;
+        uint16_t command;
+        uint16_t status;
+        uint8_t revision;
+        uint8_t progIF;
+        uint8_t subClassCode;
+        uint8_t classCode;
+        uint8_t cacheLineSize;
+        uint8_t latencyTimer;
+        uint8_t headerType;
+        uint8_t bist;
         union {
-            struct {
-                uint32_t	baseAddr0;
-                uint32_t	baseAddr1;
-                uint32_t	baseAddr2;
-                uint32_t	baseAddr3;
-                uint32_t	baseAddr4;
-                uint32_t	baseAddr5;
-                uint32_t	cardbusCIS;
-                uint16_t	subsystemVendorID;
-                uint16_t	subsystemID;
-                uint32_t	expansionROM;
-                uint32_t	reserved0;
-                uint32_t	reserved1;
-                uint8_t		interruptLine;
-                uint8_t		interruptPin;
-                uint8_t		minimumGrant;
-                uint8_t		maximumLatency;
-            } pci0;
+            uint32_t baseAddr[6];
 
             struct {
-                uint32_t	baseAddr0;
-                uint32_t	baseAddr1;
-                uint8_t		priBusNum;
-                uint8_t		secBusNum;
-                uint8_t		subBusNum;
-                uint8_t		secLatency;
-                uint8_t		ioBase;
-                uint8_t		minimumGrantioLimit;
-                uint16_t	secStatus;
-                uint16_t	memBase;
-                uint16_t	memLimit;
-                uint16_t	prefetchMemBase;
-                uint16_t	prefetchMemLimit;
-                uint32_t	prfBaseUpper32;
-                uint32_t	prfLimitUpper32;
-                uint16_t	ioBaseUpper16;
-                uint16_t	ioLimitUpper16;
-                uint32_t	reserved0;
-                uint32_t	expansionROM;
-                uint8_t		interruptLine;
-                uint8_t		interruptPin;
-                uint16_t	bridgeControl;
-            } pci1;
+                uint32_t baseAddr0;
+                uint32_t baseAddr1;
+                uint32_t baseAddr2;
+                uint32_t baseAddr3;
+                uint32_t baseAddr4;
+                uint32_t baseAddr5;
+            };
         };
-    } hdr;
+        uint32_t cardbusCIS;
+        uint16_t subsystemVendorID;
+        uint16_t subsystemID;
+        uint32_t expansionROM;
+        uint32_t reserved0;
+        uint32_t reserved1;
+        uint8_t interruptLine;
+        uint8_t interruptPin;
+        uint8_t minimumGrant;
+        uint8_t maximumLatency;
+    };
 };
 
 // Common PCI offsets