Changes for getting FreeBSD to run.

SConscript:
    Added more files to compile: dev/pcifake.cc, dev/isa_fake.cc, kern/freebsd/freebsd_system.cc, kern/freebsd/freebsd_events.cc.
arch/alpha/isa_traits.hh:
    Added constant for argument register 2 as it is needed by FreebsdSystem::doCalibrateClocks().
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
    Replaced htoa()s with gtoh() and htog().
cpu/o3/fetch_impl.hh:
cpu/simple/cpu.cc:
    Replaced htoa() with gtoh().
dev/disk_image.cc:
    Replaced htoa()s with letoh()s.
dev/ide_ctrl.cc:
    Got rid of magic numbers.
    Added IdeChannel and IdeRegType type names where necessary.
dev/ide_ctrl.hh:
    Got rid of unnecessary macros.
    Changed RegType_t to IdeRegType.
    Changed bmi_regs to allow accessing registers by name instead of just by array index.
    Added IdeChannel enum type to use in place of bool variables which were used to specify IDE channel.
dev/ide_disk.cc:
    Rewrote IdeDisk::read and IdeDisk::write functions to specify registers by name instead of indexing through an array.
dev/ide_disk.hh:
    Updated command register struct.
dev/ns_gige.cc:
dev/ns_gige.hh:
    Made ReadConfig and WriteConfig begin with a lower-case letter.
    writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pciconfigall.cc:
    writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pcidev.cc:
    Cleaned up readConfig() and writeConfig() functions.
dev/pcidev.hh:
    Added macros to make code that works with the BARs (base adress registers) more readable. writeConfig() now takes a pointer to data.
dev/pcireg.h:
    Changed PCIConfig struct to make accessing elements more straight forward. Removed type 1 (for PCI-to-PCI bridges) PCI configuration space struct since it is not used.
dev/rtcreg.h:
    Added macros for bit fields in RTC status registers A & B.
dev/sinic.cc:
    Function name change: WriteConfig --> writeConfig.
    writeConfig() now takes a pointer to data instead of a copy of data.
    The accessing of elements of PCIConfig structure is updated.
dev/sinic.hh:
    Function name change: WriteConfig --> writeConfig.
    writeConfig() now takes a pointer to data instead of a copy of data.
dev/tsunami_io.cc:
    Added implementation of new RTC and PIT classes.
dev/tsunami_io.hh:
    Added classes for RTC and PIT modules.
dev/tsunamireg.h:
    Added macros for DMA ports used by Tsunami-Tru64.
dev/uart8250.cc:
    Got rid of a magic number.
    Transmit (Tx) interrupts should clear upon a read of the Interrupt ID register.
dev/uart8250.hh:
    Added comments and macros dealing with the UART Interrupt ID register.
kern/linux/linux_system.cc:
    Replaced htoa() with htog().
python/m5/objects/Pci.py:
    PciFake is a python class for Pci Devices that do nothing.
python/m5/objects/Tsunami.py:
    TsunamiFake was renamed as IsaFake.
sim/system.cc:
    Replaced htoa()s with htog()s.
dev/isa_fake.cc:
    New BitKeeper file ``dev/isa_fake.cc''
    TsunamiFake was renamed as IsaFake.
dev/isa_fake.hh:
    New BitKeeper file ``dev/isa_fake.hh''
    TsunmaiFake was renamed as IsaFake.
dev/pitreg.h:
    New BitKeeper file ``dev/pitreg.h''
    Useful macros for working with PIT (Periodic Interval Timer) registers.

--HG--
extra : convert_revision : 33f3a8a1034af4f6c71b32dd743e371c8613e780

1 files changed, 18 insertions, 4 deletions

diff --git a/dev/rtcreg.h b/dev/rtcreg.h
index 0b33c25b2..5025a0e95 100644
--- a/dev/rtcreg.h
+++ b/dev/rtcreg.h
@@ -36,8 +36,22 @@
 #define RTC_DOM                 0x07
 #define RTC_MON                 0x08
 #define RTC_YEAR                0x09
-#define RTC_CNTRL_REGA          0x0A
-#define RTC_CNTRL_REGB          0x0B
-#define RTC_CNTRL_REGC          0x0C
-#define RTC_CNTRL_REGD          0x0D
+
+#define RTC_STAT_REGA           0x0A
+#define  RTCA_1024HZ            0x06  /* 1024Hz periodic interrupt frequency */
+#define  RTCA_32768HZ           0x20  /* 22-stage divider, 32.768KHz timebase */
+#define  RTCA_UIP               0x80  /* 1 = date and time update in progress */
+
+#define RTC_STAT_REGB           0x0B
+#define  RTCB_DST               0x01  /* USA Daylight Savings Time enable */
+#define  RTCB_24HR              0x02  /* 0 = 12 hours, 1 = 24 hours */
+#define  RTCB_BIN               0x04  /* 0 = BCD, 1 = Binary coded time */
+#define  RTCB_SQWE              0x08  /* 1 = output sqare wave at SQW pin */
+#define  RTCB_UPDT_IE           0x10  /* 1 = enable update-ended interrupt */
+#define  RTCB_ALRM_IE           0x20  /* 1 = enable alarm interrupt */
+#define  RTCB_PRDC_IE           0x40  /* 1 = enable periodic clock interrupt */
+#define  RTCB_NO_UPDT           0x80  /* stop clock updates */
+
+#define RTC_STAT_REGC           0x0C
+#define RTC_STAT_REGD           0x0D