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author | Gabe Black <gblack@eecs.umich.edu> | 2006-02-16 01:25:48 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-02-16 01:25:48 -0500 |
commit | b161d2a731ec7d75bdeb896d1b89efcbb125a09f (patch) | |
tree | a1a92378afb4d05e8c9e2d047c1c9edbcc9e3447 /dev/sinic.cc | |
parent | 7f17f1f2df7dc7123448ec624a345ee7c0e996b5 (diff) | |
parent | 10c79efe556697ebbed74c82214b5505b405da5b (diff) | |
download | gem5-b161d2a731ec7d75bdeb896d1b89efcbb125a09f.tar.xz |
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch
--HG--
extra : convert_revision : d8626acb2686e123ad0bb6cf94e85c992657470d
Diffstat (limited to 'dev/sinic.cc')
-rw-r--r-- | dev/sinic.cc | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/dev/sinic.cc b/dev/sinic.cc index 69239df32..e79f80678 100644 --- a/dev/sinic.cc +++ b/dev/sinic.cc @@ -361,23 +361,23 @@ Device::prepareWrite(int cpu, int index) /** * I/O read of device register */ -Fault +Fault * Device::read(MemReqPtr &req, uint8_t *data) { assert(config.command & PCI_CMD_MSE); - Fault fault = readBar(req, data); + Fault * fault = readBar(req, data); - if (fault == Machine_Check_Fault) { + if (fault == MachineCheckFault) { panic("address does not map to a BAR pa=%#x va=%#x size=%d", req->paddr, req->vaddr, req->size); - return Machine_Check_Fault; + return MachineCheckFault; } return fault; } -Fault +Fault * Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data) { int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff; @@ -421,13 +421,13 @@ Device::readBar0(MemReqPtr &req, Addr daddr, uint8_t *data) if (raddr == Regs::IntrStatus) devIntrClear(); - return No_Fault; + return NoFault; } /** * IPR read of device register */ -Fault +Fault * Device::iprRead(Addr daddr, int cpu, uint64_t &result) { if (!regValid(daddr)) @@ -451,29 +451,29 @@ Device::iprRead(Addr daddr, int cpu, uint64_t &result) DPRINTF(EthernetPIO, "IPR read %s: cpu=%s da=%#x val=%#x\n", info.name, cpu, result); - return No_Fault; + return NoFault; } /** * I/O write of device register */ -Fault +Fault * Device::write(MemReqPtr &req, const uint8_t *data) { assert(config.command & PCI_CMD_MSE); - Fault fault = writeBar(req, data); + Fault * fault = writeBar(req, data); - if (fault == Machine_Check_Fault) { + if (fault == MachineCheckFault) { panic("address does not map to a BAR pa=%#x va=%#x size=%d", req->paddr, req->vaddr, req->size); - return Machine_Check_Fault; + return MachineCheckFault; } return fault; } -Fault +Fault * Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) { int cpu = (req->xc->regs.ipr[TheISA::IPR_PALtemp16] >> 8) & 0xff; @@ -508,7 +508,7 @@ Device::writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data) if (!pioDelayWrite || !info.delay_write) regWrite(daddr, cpu, data); - return No_Fault; + return NoFault; } void |