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authorRon Dreslinski <rdreslin@umich.edu>2005-04-29 21:01:43 -0400
committerRon Dreslinski <rdreslin@umich.edu>2005-04-29 21:01:43 -0400
commit602a489573c96d574798c622a70b1b466330fdaf (patch)
tree4df5e972b36e13a647fe29f3054c8b8a10f4e524 /dev/sinic.cc
parente07fee31cb7d3434d4ce5bb05a2a6b686f49fa50 (diff)
downloadgem5-602a489573c96d574798c622a70b1b466330fdaf.tar.xz
Add suport for no allocation of cache block on a dma read passing through a cache from the cpu-side interface
--HG-- extra : convert_revision : 0a3b3741924ed39c1c8710d0963e4c8f3e73f81a
Diffstat (limited to 'dev/sinic.cc')
-rw-r--r--dev/sinic.cc12
1 files changed, 8 insertions, 4 deletions
diff --git a/dev/sinic.cc b/dev/sinic.cc
index 9535a58ca..4d6ecf668 100644
--- a/dev/sinic.cc
+++ b/dev/sinic.cc
@@ -103,11 +103,11 @@ Device::Device(Params *p)
if (p->payload_bus)
dmaInterface = new DMAInterface<Bus>(p->name + ".dma",
p->header_bus, p->payload_bus,
- 1);
+ 1, p->dma_no_allocate);
else
dmaInterface = new DMAInterface<Bus>(p->name + ".dma",
p->header_bus, p->header_bus,
- 1);
+ 1, p->dma_no_allocate);
} else if (p->payload_bus) {
pioInterface = newPioInterface(p->name, p->hier, p->payload_bus, this,
&Device::cacheAccess);
@@ -115,7 +115,8 @@ Device::Device(Params *p)
pioLatency = p->pio_latency * p->payload_bus->clockRatio;
dmaInterface = new DMAInterface<Bus>(p->name + ".dma", p->payload_bus,
- p->payload_bus, 1);
+ p->payload_bus, 1,
+ p->dma_no_allocate);
}
}
@@ -1388,6 +1389,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Device)
Param<Tick> dma_read_factor;
Param<Tick> dma_write_delay;
Param<Tick> dma_write_factor;
+ Param<bool> dma_no_allocate;
END_DECLARE_SIM_OBJECT_PARAMS(Device)
@@ -1421,7 +1423,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Device)
INIT_PARAM_DFLT(dma_read_delay, "fixed delay for dma reads", 0),
INIT_PARAM_DFLT(dma_read_factor, "multiplier for dma reads", 0),
INIT_PARAM_DFLT(dma_write_delay, "fixed delay for dma writes", 0),
- INIT_PARAM_DFLT(dma_write_factor, "multiplier for dma writes", 0)
+ INIT_PARAM_DFLT(dma_write_factor, "multiplier for dma writes", 0),
+ INIT_PARAM_DFLT(dma_no_allocate, "Should we allocat on read in cache", true)
END_INIT_SIM_OBJECT_PARAMS(Device)
@@ -1458,6 +1461,7 @@ CREATE_SIM_OBJECT(Device)
params->dma_read_factor = dma_read_factor;
params->dma_write_delay = dma_write_delay;
params->dma_write_factor = dma_write_factor;
+ params->dma_no_allocate = dma_no_allocate;
return new Device(params);
}