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authorGabe Black <gblack@eecs.umich.edu>2006-02-27 03:57:15 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-02-27 03:57:15 -0500
commit444f520f7e2da9468fa622dcf51859915bd31fd6 (patch)
tree5d5a217fcc16fe1b89c9625867a54ef87c499813 /dev/sinic.cc
parent1a0b326f5d4fafaef206a97ddd02598e120aebb9 (diff)
downloadgem5-444f520f7e2da9468fa622dcf51859915bd31fd6.tar.xz
MachineCheckFaults and AlignmentFaults are now generated by the ISA, rather than being created directly.
arch/alpha/alpha_memory.cc: cpu/base_dyn_inst.cc: dev/alpha_console.cc: dev/pcidev.hh: dev/sinic.cc: MachineCheckFaults are now generated by the ISA, rather than being created directly. --HG-- extra : convert_revision : 34a7da41639e93be21ed70dac681b27480008d19
Diffstat (limited to 'dev/sinic.cc')
-rw-r--r--dev/sinic.cc8
1 files changed, 4 insertions, 4 deletions
diff --git a/dev/sinic.cc b/dev/sinic.cc
index 3f7226817..ba643de4b 100644
--- a/dev/sinic.cc
+++ b/dev/sinic.cc
@@ -363,11 +363,11 @@ Device::read(MemReqPtr &req, uint8_t *data)
assert(config.command & PCI_CMD_MSE);
Fault fault = readBar(req, data);
- if (fault->isA<MachineCheckFault>()) {
+ if (fault->isMachineCheckFault()) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
req->paddr, req->vaddr, req->size);
- return new MachineCheckFault;
+ return genMachineCheckFault();
}
return fault;
@@ -459,11 +459,11 @@ Device::write(MemReqPtr &req, const uint8_t *data)
assert(config.command & PCI_CMD_MSE);
Fault fault = writeBar(req, data);
- if (fault->isA<MachineCheckFault>()) {
+ if (fault->isMachineCheckFault()) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
req->paddr, req->vaddr, req->size);
- return new MachineCheckFault;
+ return genMachineCheckFault();
}
return fault;