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author | Gabe Black <gblack@eecs.umich.edu> | 2006-02-16 01:25:48 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-02-16 01:25:48 -0500 |
commit | b161d2a731ec7d75bdeb896d1b89efcbb125a09f (patch) | |
tree | a1a92378afb4d05e8c9e2d047c1c9edbcc9e3447 /dev/sinic.hh | |
parent | 7f17f1f2df7dc7123448ec624a345ee7c0e996b5 (diff) | |
parent | 10c79efe556697ebbed74c82214b5505b405da5b (diff) | |
download | gem5-b161d2a731ec7d75bdeb896d1b89efcbb125a09f.tar.xz |
Merge gblack@m5.eecs.umich.edu:/bk/multiarch
into ewok.(none):/home/gblack/m5/multiarch
--HG--
extra : convert_revision : d8626acb2686e123ad0bb6cf94e85c992657470d
Diffstat (limited to 'dev/sinic.hh')
-rw-r--r-- | dev/sinic.hh | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/dev/sinic.hh b/dev/sinic.hh index af2f109a4..7935a7cdc 100644 --- a/dev/sinic.hh +++ b/dev/sinic.hh @@ -271,15 +271,15 @@ class Device : public Base * Memory Interface */ public: - virtual Fault read(MemReqPtr &req, uint8_t *data); - virtual Fault write(MemReqPtr &req, const uint8_t *data); + virtual Fault * read(MemReqPtr &req, uint8_t *data); + virtual Fault * write(MemReqPtr &req, const uint8_t *data); void prepareIO(int cpu, int index); void prepareRead(int cpu, int index); void prepareWrite(int cpu, int index); - Fault iprRead(Addr daddr, int cpu, uint64_t &result); - Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data); - Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data); + Fault * iprRead(Addr daddr, int cpu, uint64_t &result); + Fault * readBar0(MemReqPtr &req, Addr daddr, uint8_t *data); + Fault * writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data); void regWrite(Addr daddr, int cpu, const uint8_t *data); Tick cacheAccess(MemReqPtr &req); |