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| author | Gabe Black <gblack@eecs.umich.edu> | 2006-02-28 06:03:57 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-02-28 06:03:57 -0500 |
| commit | d207168eda13483a2990cdf060c1a7ead42cc9da (patch) | |
| tree | 18383564b534a5fe6a7ba73bdc179fa249788013 /dev/sinic.hh | |
| parent | e5f75c2549d4881284202208c09e881886f4fdd4 (diff) | |
| parent | 29f50d934549f10b073a5492bd0d441d71534ace (diff) | |
| download | gem5-d207168eda13483a2990cdf060c1a7ead42cc9da.tar.xz | |
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
--HG--
extra : convert_revision : 3a3ff8fcf472db385219a00ae434d1f3fea43b18
Diffstat (limited to 'dev/sinic.hh')
| -rw-r--r-- | dev/sinic.hh | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/dev/sinic.hh b/dev/sinic.hh index 97ebf4c30..c4027be86 100644 --- a/dev/sinic.hh +++ b/dev/sinic.hh @@ -280,7 +280,6 @@ class Device : public Base Fault iprRead(Addr daddr, int cpu, uint64_t &result); Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data); Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data); - void regWrite(Addr daddr, int cpu, const uint8_t *data); Tick cacheAccess(MemReqPtr &req); /** |