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| author | Nathan Binkert <binkertn@umich.edu> | 2006-02-25 22:01:05 -0500 |
|---|---|---|
| committer | Nathan Binkert <binkertn@umich.edu> | 2006-02-25 22:01:05 -0500 |
| commit | 25b39da69d4267b34a87b7324008b6d4480a2b09 (patch) | |
| tree | 18482c42a9e9f504ecacb111d766d88681fcd177 /dev/sinic.hh | |
| parent | 4d01be373e8eeb634b8350fe3bfecd195133a8f5 (diff) | |
| download | gem5-25b39da69d4267b34a87b7324008b6d4480a2b09.tar.xz | |
Since the delayed write stuff is gone, get rid of regWrite
and merge it with writeBar0
--HG--
extra : convert_revision : 354642e0d528b6a5a7f2cdf0264d93e738b2d4eb
Diffstat (limited to 'dev/sinic.hh')
| -rw-r--r-- | dev/sinic.hh | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/dev/sinic.hh b/dev/sinic.hh index 97ebf4c30..c4027be86 100644 --- a/dev/sinic.hh +++ b/dev/sinic.hh @@ -280,7 +280,6 @@ class Device : public Base Fault iprRead(Addr daddr, int cpu, uint64_t &result); Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data); Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data); - void regWrite(Addr daddr, int cpu, const uint8_t *data); Tick cacheAccess(MemReqPtr &req); /** |