Shuffle around device names to make things easier to read.

Create EtherDevBase which both Sinic and NSGigE derive from
bump fifos
drop rx max copy size to 1514 bytes to be friendlier with linux
default interrupt delay is 10us

dev/ns_gige.cc:
    Shuffle around parameters to make it easier to find stuff
dev/sinic.cc:
    Shuffle around parameters to make it easier to find stuff
    rename cycleTime -> clock
dev/sinic.hh:
    rename cycleTime -> clock

--HG--
extra : convert_revision : a673bee875e50d083098991aea20972fa8d5b5c7

1 files changed, 3 insertions, 3 deletions

diff --git a/dev/sinic.hh b/dev/sinic.hh
index d190746a4..924c6eeeb 100644
--- a/dev/sinic.hh
+++ b/dev/sinic.hh
@@ -48,8 +48,8 @@ class Base : public PciDev
   protected:
     bool rxEnable;
     bool txEnable;
-    Tick cycleTime;
-    inline Tick cycles(int numCycles) const { return numCycles * cycleTime; }
+    Tick clock;
+    inline Tick cycles(int numCycles) const { return numCycles * clock; }
 
   protected:
     Tick intrDelay;
@@ -81,7 +81,7 @@ class Base : public PciDev
   public:
     struct Params : public PciDev::Params
     {
-        Tick cycle_time;
+        Tick clock;
         Tick intr_delay;
     };