Mostly done with all device models for new memory system. Still need to get timing packets working and get sinic working

after merge from head. Checkpointing may need some work now. Endian-happiness still not complete.

SConscript:
    add all devices back into make file
base/inet.hh:
dev/etherbus.cc:
dev/etherbus.hh:
dev/etherdump.cc:
dev/etherdump.hh:
dev/etherint.hh:
dev/etherlink.cc:
dev/etherlink.hh:
dev/etherpkt.cc:
dev/etherpkt.hh:
dev/ethertap.cc:
dev/ethertap.hh:
dev/pktfifo.cc:
dev/pktfifo.hh:
    rename PacketPtr EthPacketPtr so it doesn't conflict with the PacketPtr type in the memory system
configs/test/fs.py:
    add nics to fs.py
cpu/cpu_exec_context.cc:
    remove this check, as it's not valid. We may want to add something else back in to make sure that no one can delete the
    static virtual ports in the exec context
cpu/simple/cpu.cc:
cpu/simple/cpu.hh:
dev/alpha_console.cc:
dev/ide_ctrl.cc:
    use new methods for accessing packet data
dev/ide_disk.cc:
    add some more dprintfs
dev/io_device.cc:
    delete packets when we are done with them. Update for new packet methods to access data
dev/isa_fake.cc:
dev/pciconfigall.cc:
dev/tsunami_cchip.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart8250.cc:
dev/uart8250.hh:
mem/physical.cc:
mem/port.cc:
    dUpdate for new packet methods to access data
dev/ns_gige.cc:
    Update for new memory system
dev/ns_gige.hh:
python/m5/objects/Ethernet.py:
    update for new memory system
dev/sinic.cc:
dev/sinic.hh:
    Update for new memory system. Untested as need to merge in head because of kernel driver differences between versions
mem/packet.hh:
    Add methods to access data instead of accessing it directly.

--HG--
extra : convert_revision : 223f43876afd404e68337270cd9a5e44d0bf553e

1 files changed, 7 insertions, 37 deletions

diff --git a/dev/sinic.hh b/dev/sinic.hh
index 25172fa45..63a8585dc 100644
--- a/dev/sinic.hh
+++ b/dev/sinic.hh
@@ -37,7 +37,6 @@
 #include "dev/pcidev.hh"
 #include "dev/pktfifo.hh"
 #include "dev/sinicreg.hh"
-#include "mem/bus/bus.hh"
 #include "sim/eventq.hh"
 
 namespace Sinic {
@@ -91,10 +90,6 @@ class Base : public PciDev
 class Device : public Base
 {
   protected:
-    Platform *plat;
-    PhysicalMemory *physmem;
-
-  protected:
     /** Receive State Machine States */
     enum RxState {
         rxIdle,
@@ -162,10 +157,6 @@ class Device : public Base
     uint32_t &regData32(Addr daddr) { return *(uint32_t *)&regData8(daddr); }
     uint64_t &regData64(Addr daddr) { return *(uint64_t *)&regData8(daddr); }
 
-  private:
-    Addr addr;
-    static const Addr size = Regs::Size;
-
   protected:
     RxState rxState;
     PacketFifo rxFifo;
@@ -178,7 +169,7 @@ class Device : public Base
     TxState txState;
     PacketFifo txFifo;
     bool txFull;
-    PacketPtr txPacket;
+    EthPacketPtr txPacket;
     int txPacketOffset;
     int txPacketBytes;
     Addr txDmaAddr;
@@ -218,7 +209,7 @@ class Device : public Base
     /**
      * receive address filter
      */
-    bool rxFilter(const PacketPtr &packet);
+    bool rxFilter(const EthPacketPtr &packet);
 
 /**
  * device configuration
@@ -230,7 +221,7 @@ class Device : public Base
  * device ethernet interface
  */
   public:
-    bool recvPacket(PacketPtr packet);
+    bool recvPacket(EthPacketPtr packet);
     void transferDone();
     void setInterface(Interface *i) { assert(!interface); interface = i; }
 
@@ -238,12 +229,10 @@ class Device : public Base
  * DMA parameters
  */
   protected:
-    void rxDmaCopy();
     void rxDmaDone();
     friend class EventWrapper<Device, &Device::rxDmaDone>;
     EventWrapper<Device, &Device::rxDmaDone> rxDmaEvent;
 
-    void txDmaCopy();
     void txDmaDone();
     friend class EventWrapper<Device, &Device::txDmaDone>;
     EventWrapper<Device, &Device::txDmaDone> txDmaEvent;
@@ -262,25 +251,16 @@ class Device : public Base
     void devIntrChangeMask(uint32_t newmask);
 
 /**
- * PCI Configuration interface
- */
-  public:
-    virtual void writeConfig(int offset, int size, const uint8_t *data);
-
-/**
  * Memory Interface
  */
   public:
-    virtual Fault read(MemReqPtr &req, uint8_t *data);
-    virtual Fault write(MemReqPtr &req, const uint8_t *data);
+    virtual Tick read(Packet &pkt);
+    virtual Tick write(Packet &pkt);
 
     void prepareIO(int cpu, int index);
     void prepareRead(int cpu, int index);
     void prepareWrite(int cpu, int index);
-    Fault iprRead(Addr daddr, int cpu, uint64_t &result);
-    Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
-    Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
-    Tick cacheAccess(MemReqPtr &req);
+ //   Fault iprRead(Addr daddr, int cpu, uint64_t &result);
 
 /**
  * Statistics
@@ -328,17 +308,8 @@ class Device : public Base
   public:
     struct Params : public Base::Params
     {
-        IntrControl *i;
-        PhysicalMemory *pmem;
         Tick tx_delay;
         Tick rx_delay;
-        HierParams *hier;
-        Bus *pio_bus;
-        Bus *header_bus;
-        Bus *payload_bus;
-        Tick pio_latency;
-        PhysicalMemory *physmem;
-        IntrControl *intctrl;
         bool rx_filter;
         Net::EthAddr eaddr;
         uint32_t rx_max_copy;
@@ -352,7 +323,6 @@ class Device : public Base
         Tick dma_read_factor;
         Tick dma_write_delay;
         Tick dma_write_factor;
-        bool dma_no_allocate;
         bool rx_thread;
         bool tx_thread;
         bool rss;
@@ -378,7 +348,7 @@ class Interface : public EtherInt
     Interface(const std::string &name, Device *d)
         : EtherInt(name), dev(d) { dev->setInterface(this); }
 
-    virtual bool recvPacket(PacketPtr pkt) { return dev->recvPacket(pkt); }
+    virtual bool recvPacket(EthPacketPtr pkt) { return dev->recvPacket(pkt); }
     virtual void sendDone() { dev->transferDone(); }
 };