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authorGabe Black <gblack@eecs.umich.edu>2006-02-21 20:10:40 -0500
committerGabe Black <gblack@eecs.umich.edu>2006-02-21 20:10:40 -0500
commit8d80fd1477fa39ebc5bad4ca5c727b2871fd9b8d (patch)
treeaa785d4b846823e1960c7b308e6de1c90cf6fb3f /dev/sinic.hh
parent3f7979c99d8dc4f434e3daa2e179616f1669e16e (diff)
downloadgem5-8d80fd1477fa39ebc5bad4ca5c727b2871fd9b8d.tar.xz
Changed Fault * to Fault, which is a typedef to FaultBase *, which is the old Fault class renamed.
--HG-- extra : convert_revision : 5b2f457401f8ff94fe39fe071288eb117814b7bb
Diffstat (limited to 'dev/sinic.hh')
-rw-r--r--dev/sinic.hh10
1 files changed, 5 insertions, 5 deletions
diff --git a/dev/sinic.hh b/dev/sinic.hh
index 06751a955..97ebf4c30 100644
--- a/dev/sinic.hh
+++ b/dev/sinic.hh
@@ -271,15 +271,15 @@ class Device : public Base
* Memory Interface
*/
public:
- virtual Fault * read(MemReqPtr &req, uint8_t *data);
- virtual Fault * write(MemReqPtr &req, const uint8_t *data);
+ virtual Fault read(MemReqPtr &req, uint8_t *data);
+ virtual Fault write(MemReqPtr &req, const uint8_t *data);
void prepareIO(int cpu, int index);
void prepareRead(int cpu, int index);
void prepareWrite(int cpu, int index);
- Fault * iprRead(Addr daddr, int cpu, uint64_t &result);
- Fault * readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
- Fault * writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
+ Fault iprRead(Addr daddr, int cpu, uint64_t &result);
+ Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
+ Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
void regWrite(Addr daddr, int cpu, const uint8_t *data);
Tick cacheAccess(MemReqPtr &req);