diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2006-02-20 23:55:25 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-02-20 23:55:25 -0500 |
| commit | 74d7cd1ceadd8ba803bbb83750e11a3c488d3fe1 (patch) | |
| tree | bb1cfdce0b5c1d2b0acef8d38c08b15d49616327 /dev/sinic.hh | |
| parent | 466284b5d29ad0d44c1b020353cf7521be2b90de (diff) | |
| parent | 3a0102536bdbf00629e6ba944bd55ee0ec77fb52 (diff) | |
| download | gem5-74d7cd1ceadd8ba803bbb83750e11a3c488d3fe1.tar.xz | |
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
into zizzer.eecs.umich.edu:/z/m5/Bitkeeper/multiarch
--HG--
extra : convert_revision : da72b3593037c2a67a56c799e292853b8aece907
Diffstat (limited to 'dev/sinic.hh')
| -rw-r--r-- | dev/sinic.hh | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/dev/sinic.hh b/dev/sinic.hh index 7935a7cdc..06751a955 100644 --- a/dev/sinic.hh +++ b/dev/sinic.hh @@ -283,17 +283,6 @@ class Device : public Base void regWrite(Addr daddr, int cpu, const uint8_t *data); Tick cacheAccess(MemReqPtr &req); - protected: - struct RegWriteData { - Addr daddr; - uint64_t value; - RegWriteData(Addr da, uint64_t val) : daddr(da), value(val) {} - }; - - std::vector<std::list<RegWriteData> > writeQueue; - - bool pioDelayWrite; - /** * Statistics */ @@ -349,7 +338,6 @@ class Device : public Base Bus *header_bus; Bus *payload_bus; Tick pio_latency; - bool pio_delay_write; PhysicalMemory *physmem; IntrControl *intctrl; bool rx_filter; |