Major update to sinic to support VSINIC better

dev/sinic.cc:
    - Size the virtualRegs array based on the configured value
    - Add debugging stuff for uniquely identifying vnic usage
    - Only count totally unprocessed packets when notifying via RxDone
    - Add initial virtual address support
    - Fix some bugs in accessing packets out of order to make sure that
    busy packets are processed first
    - Add fifo watermark stuff
    - Make number of vnics, zero/delay copy and watermarks parameters
dev/sinic.hh:
    add rxUnique and txUnique to uniquely identify tx and rx VNICs
    Create a separate list of Busy VNICs since more than one might
    be busy and we want to service those first
    Add more watermark stuff and new parameters
dev/sinicreg.hh:
    Make the number of virtual nics a read-only parameter
    add bits for ZeroCopy/DelayCopy
    rename Virtual to Vaddr so it's not ambiguous
    Add a flag for TxData/RxData to indicate a virtual address
    Report rxfifo status in RxDone
python/m5/objects/Ethernet.py:
    add more options for the fifo thresholds
    add number of vnics as a parameter
    add copy type as a parameter
    add virtual addressing as a parameter

--HG--
extra : convert_revision : 850e2433b585d65469d4c5d85ad7ca820db10f4a

1 files changed, 15 insertions, 1 deletions

diff --git a/dev/sinic.hh b/dev/sinic.hh
index 25172fa45..892b3ab69 100644
--- a/dev/sinic.hh
+++ b/dev/sinic.hh
@@ -122,7 +122,7 @@ class Device : public Base
         uint32_t RxMaxCopy;    // 0x10
         uint32_t TxMaxCopy;    // 0x14
         uint32_t RxMaxIntr;    // 0x18
-        uint32_t Reserved0;    // 0x1c
+        uint32_t VirtualCount; // 0x1c
         uint32_t RxFifoSize;   // 0x20
         uint32_t TxFifoSize;   // 0x24
         uint32_t RxFifoMark;   // 0x28
@@ -147,6 +147,9 @@ class Device : public Base
         int rxPacketBytes;
         uint64_t rxDoneData;
 
+        Counter rxUnique;
+        Counter txUnique;
+
         VirtualReg()
             : RxData(0), RxDone(0), TxData(0), TxDone(0),
               rxPacketOffset(0), rxPacketBytes(0), rxDoneData(0)
@@ -154,8 +157,12 @@ class Device : public Base
     };
     typedef std::vector<VirtualReg> VirtualRegs;
     typedef std::list<int> VirtualList;
+    Counter rxUnique;
+    Counter txUnique;
     VirtualRegs virtualRegs;
     VirtualList rxList;
+    VirtualList rxBusy;
+    int rxActive;
     VirtualList txList;
 
     uint8_t  &regData8(Addr daddr) { return *((uint8_t *)&regs + daddr); }
@@ -171,6 +178,7 @@ class Device : public Base
     PacketFifo rxFifo;
     PacketFifo::iterator rxFifoPtr;
     bool rxEmpty;
+    bool rxLow;
     Addr rxDmaAddr;
     uint8_t *rxDmaData;
     int rxDmaLen;
@@ -347,6 +355,8 @@ class Device : public Base
         uint32_t rx_fifo_size;
         uint32_t tx_fifo_size;
         uint32_t rx_fifo_threshold;
+        uint32_t rx_fifo_low_mark;
+        uint32_t tx_fifo_high_mark;
         uint32_t tx_fifo_threshold;
         Tick dma_read_delay;
         Tick dma_read_factor;
@@ -356,6 +366,10 @@ class Device : public Base
         bool rx_thread;
         bool tx_thread;
         bool rss;
+        uint32_t virtual_count;
+        bool zero_copy;
+        bool delay_copy;
+        bool virtual_addr;
     };
 
   protected: