add support for delaying pio writes until the cache access occurs

dev/ns_gige.cc:
    add support for delaying pio writes until the cache access occurs
    the only write we delay are for CR_TXE and CR_RXE
dev/sinic.cc:
dev/sinic.hh:
    the txPioRequest and rxPioRequest things were more or less bogus
    add support for delaying pio writes until the cache access occurs
dev/sinicreg.hh:
    Add delay_read and delay_write to the register information struct
    for now, we won't delay any reads, and we'll delay the writes that
    initiate DMAs
python/m5/objects/Ethernet.py:
    add a parameter to delay pio writes until the timing access
    actually occurs.

--HG--
extra : convert_revision : 79b18ea2812c2935d7d5ea6eff1f55265114d05d

1 files changed, 17 insertions, 9 deletions

diff --git a/dev/sinic.hh b/dev/sinic.hh
index b9089cd53..b3255b6c0 100644
--- a/dev/sinic.hh
+++ b/dev/sinic.hh
@@ -235,13 +235,6 @@ class Device : public Base
     Tick dmaWriteFactor;
 
 /**
- * PIO parameters
- */
-  protected:
-    MemReqPtr rxPioRequest;
-    MemReqPtr txPioRequest;
-
-/**
  * Interrupt management
  */
   protected:
@@ -262,12 +255,26 @@ class Device : public Base
     virtual Fault read(MemReqPtr &req, uint8_t *data);
     virtual Fault write(MemReqPtr &req, const uint8_t *data);
 
-    void prepareRead();
-    Fault iprRead(Addr daddr, uint64_t &result);
+    void prepareIO(int cpu);
+    void prepareRead(int cpu);
+    void prepareWrite(int cpu);
+    Fault iprRead(Addr daddr, int cpu, uint64_t &result);
     Fault readBar0(MemReqPtr &req, Addr daddr, uint8_t *data);
     Fault writeBar0(MemReqPtr &req, Addr daddr, const uint8_t *data);
+    void regWrite(Addr daddr, int cpu, const uint8_t *data);
     Tick cacheAccess(MemReqPtr &req);
 
+  protected:
+    struct RegWriteData {
+        Addr daddr;
+        uint64_t value;
+        RegWriteData(Addr da, uint64_t val) : daddr(da), value(val) {}
+    };
+
+    std::vector<std::list<RegWriteData> > writeQueue;
+
+    bool pioDelayWrite;
+
 /**
  * Statistics
  */
@@ -323,6 +330,7 @@ class Device : public Base
         Bus *header_bus;
         Bus *payload_bus;
         Tick pio_latency;
+        bool pio_delay_write;
         PhysicalMemory *physmem;
         IntrControl *intctrl;
         bool rx_filter;